cpe229_lec06

cpe229_lec06 - CPE 229 Course Notes Lecture 6 Copyright...

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CPE 229 Course Notes: Lecture 6 Copyright: 2005 Bryan Mealy Finite State Machine Design Using VHDL At this point in your digital design career, you’ve probably designed many Finite State Machines (FSMs) on paper, but there was no real point for the design. In the unfortunate case where you’re actually required to implement a FSM design in real hardware, you’ll want to have the tools to do so without doing too much work on paper. Implementing FSMs in VHDL is straight-forward using a continuation of the “new” FSM techniques 1 but there is arguably a better way. The approach introduced in this set of notes takes full advantage of the behavioral modeling capabilities of VHDL. As you have probably have noticed by now, any time that you are able to implement a circuit by describing its behavior (as opposed to describing the actually logic used to implement the behavior), you’ll be allowing the VHDL synthesis process to do most of the grunt-work that is usually required of the circuit designer (especially the student circuit designer). The ugly secret behind all of this is that once you understand these techniques, you’ll be able to quickly apply them to any FSM problem that actually requires implementation. This approach is so straight-forward that it’s almost a template approach (can you say cookie-cutter?) to implementing FSMs. Yes, there you may find yourself in a situation sometime in your life where you’re forced to implement a FSM using a bunch of JK flip-flops on SSI ICs (small-scale integration integrated circuits) but… there may also be a day in your life where you’re struck by a comet too. But before we start on this, as usual, there are a few things that are arguably worth noting. The behavioral approach to FSM design reduces the many opportunities for errors associated with the “new” FSM techniques approach (and the classical FSM techniques). Although the new FSM techniques were interesting and instructive, it was prone to error due to the dropping of an overbar or a condition here or there. The behavioral approach allows to you go from the state diagram to VHDL code: no equation generation is necessary. All that is required is a good eye for state diagrams and a solid understanding of VHDL behavior modeling concepts. Current CPE 229 students are known world-wide to posses both of these valuable traits. Raw excitement is definitely headed your way. What makes this approach a cookie-cutter approach is by understanding each part of the “template” approach that is presented. The good news is that there are not that too many parts to understand. And, the effort you put into understanding these parts is an investment in understanding VHDL and digital circuit design in general. What a deal. The technique that follows is not the only method out there for implementing FSM using VHDL.
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cpe229_lec06 - CPE 229 Course Notes Lecture 6 Copyright...

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