cpe229_lec16 - CPE 229 Course Notes: Lecture 16 Copyright:...

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CPE 229 Course Notes: Lecture 16 Copyright: 2006 Bryan Mealy VHDL Modeling and ALUs ALUs can be implemented in a number of different ways. The approach we took in an earlier set of notes was a fairly low-level hardware-based approach. Although there was a lot to be said for this approach, it was not the optimal approach by any means. As a matter of fact, it is doubtful there is an approach that is optimal for all ALUs. Like many of the circuits we design in CPE 229, the approach we took to the ALU was to become aware of some of the ins and outs the hardware. This set of notes moves that another step towards reality with a step-by-step modeling of the VHDL ALU we spoke of (we never actually implemented it) in the simple computer we developed in class. For our CPE 229 purposes, the VHDL modeling approach to ALU implementations is nicely adequate. There are actually three main themes to this approach. The first theme is a basic exercise in digital design. As you’ll see, we’ll take a fairly complex circuit and implement it in a piecewise manner. So even though the circuit may appear daunting at first, the divide and conquer approach to designing this circuit will prove successful. This is of course one of the many nice things about VHDL: you can break a circuit down into pieces, implement those pieces individually, and then glue those pieces together to create an actual working circuit. The second theme of this set of notes is to fully explain the function of the Z and C flags (the zero and carry flags). We sort of glossed over it before, partially because there was a mistake in the diagram, and partially because it was somewhat of an advanced topic. After reconsidering the matter, I’m hoping you’ll agree that once you see the circuit modeled in VHDL, you’ll forever understand the true meaning of the Z and C flags. And the final theme is that fact that a system clock not explicitly used in the previous description of the ALU. This implementation of the ALU is necessarily sequential in nature because of the presence of “memory” within the ALU. More specifically, the accumulator, as well as the Z and C flags are storage elements. The storage function of these elements is synchronized to the system clock. You’ll see all these details later in this description. Doing It… Listed in Figure 1(a) is the ALU we used in the simple computer that we designed in class. Figure 1(b) shows the block diagram associated with the ALU shown in Figure 1(a). As you can see, the circuit contains seven inputs, and three outputs. All of the inputs can be considered control inputs; two of the outputs are status outputs (Z and C) and the other output (or set of outputs) is the data line. As described earlier, the data outputs necessarily need to be bi-directional outputs. The driving of these lines is controlled by the AOE signal. Although the width of the data lines and is listed as n for both of the diagrams in Figure 1, for now and ever more, let’s consider them to be eight bits. Once last comment before we start. Although you may be tempted to use structural modeling on this
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This note was uploaded on 03/27/2009 for the course CPE 229 taught by Professor Smith during the Spring '09 term at Cal Poly.

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cpe229_lec16 - CPE 229 Course Notes: Lecture 16 Copyright:...

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