BrookeECE51_04_FETs

# BrookeECE51_04_FETs - Chapter 4 Field-Effect Transistors...

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Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock

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Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i-v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Learn basic structure and mask layout for MOS transistors and circuits. Explore MOS device scaling Contrast 3 and 4 terminal device behavior. Describe sources of capacitance in MOSFETs. Explore FET modeling in SPICE.
MOS Capacitor Structure First electrode- Gate: Consists of low-resistivity material such as metal or polycrystalline silicon Second electrode- Substrate or Body: n - or p -type semiconductor Dielectric-Silicon dioxide:stable high-quality electrical insulator between gate and substrate.

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Substrate Conditions for Different Biases Accumulation V G <<V TN Depletion V G <V TN Inversion V G >V TN Accumulation Depletion Inversion
Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate MOS capacitance is non- linear function of voltage. Total capacitance in any region dictated by the separation between capacitor plates. Total capacitance modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance.

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NMOS Transistor: Structure 4 device terminals: Gate(G), Drain(D), Source(S) and Body(B). Source and drain regions form pn junctions with substrate. v SB , v DS and v GS always positive during normal operation. v SB always < v DS and v GS to reverse bias pn junctions
NMOS Transistor: Qualitative I- V Behavior V GS <<V TN : Only small leakage current flows. V GS <V TN : Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. V GS >V TN : Channel formed between source and drain. If v DS >0,, finite i D flows from drain to source. i B =0 and i G =0.

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NMOS Transistor: Triode Region Characteristics i D = K n v GS - V TN - v DS 2 v DS where, K n = K n ’W/L K n ’= μ n C ox ’’ (A/V 2 ) C ox ’’= ε ox /T ox ε ox = oxide permittivity (F/cm) T ox= oxide thickness (cm) for v GS - V TN v DS 0
NMOS Transistor: Triode Region Characteristics (contd.) Output characteristics appear to be linear. FET behaves like a gate-source voltage- controlled resistor between source and drain with R on = i D v DS v DS 0 Q - pt - 1 = 1 K n ' W L V GS - V TN - V DS ( 29 v DS 0 = 1 K n ' W L V GS - V TN

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MOSFET as Voltage-Controlled Resistor Example 1: Voltage-Controlled Attenuator v o v s
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• Fall '08
• MartinBrooke
• Transistor, saturation region, Vgs, Bias Analysis, NMOS Transistor

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