ece406f08hw1 - 4. Declare the following variables in...

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NC State University ECE 406 Fall 2008 ECE Department Design of Complex Digital Systems Homework #1 Due in class Wednesday, 9/3/08 1. Practice writing the following numbers (convert manually and rewrite as < size>’<base><number> ): a. Decimal 79 as an 8 bit binary (using _ between every four bits for readability) b. Decimal -1 as a 5 bit binary (MUST in 2’s complement format) c. 5 bit hexadecimal with all bits being unknown value d. 8 bit hexadecimal with all bits being “high-impedance” 2. Give 4 separate circuit examples (using gates, transistors, and power/ground) to generate the following 4 values (one circuit for each value) a. 1 b. 0 c. x d. z 3. Are these legal identifiers? (You just need to say “yes” or “no”) a. A b. ece406-001 c. and d. AND e. Input
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Unformatted text preview: 4. Declare the following variables in Verilog (You must use the N-1:0 convention). a. A 16-bit reg type vector variable called value . b. A parameter wordlength with integer value 5. c. A memory MEM containing 64 words of 8 bits each. d. A 6-bit wire type variable called mywire . 5. What are the basic components of a module? Which components are mandatory? Does it make sense to design a module without a port list? If yes, give an example. If no, why? 6. What would be the output of the following $display statements? a. reg [7:0] myval; myval= 16'hbeef; $display(The current value of myval = %b\n, myval); b. `define MAX 5d6 $display(&quot;MAX= %b\n&quot;, `MAX);- 1 -...
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This note was uploaded on 03/30/2009 for the course ECE 406 taught by Professor Davis during the Spring '08 term at N.C. State.

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