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Unformatted text preview: 4. Declare the following variables in Verilog (You must use the N-1:0 convention). a. A 16-bit reg type vector variable called value . b. A parameter wordlength with integer value 5. c. A memory MEM containing 64 words of 8 bits each. d. A 6-bit wire type variable called mywire . 5. What are the basic components of a module? Which components are mandatory? Does it make sense to design a module without a port list? If yes, give an example. If no, why? 6. What would be the output of the following $display statements? a. reg [7:0] myval; myval= 16'hbeef; $display(The current value of myval = %b\n, myval); b. `define MAX 5d6 $display("MAX= %b\n", `MAX);- 1 -...
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This note was uploaded on 03/30/2009 for the course ECE 406 taught by Professor Davis during the Spring '08 term at N.C. State.
- Spring '08