ece406f08hw2

ece406f08hw2 - addr_dec8 using only elemental logic...

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NC State University ECE 406 Fall 2008 ECE Department Design of Complex Digital Systems Homework #2 Due: 9/10/2008 1. A 4-to-1 multiplexer selects one of four input lines to pass through to a single output line. The selection is controlled by a 2-bit control input. s1 s0 z 0 0 i0 0 1 i1 1 0 i2 1 1 i3 a. (5 points) Write a Verilog description of the 4-to-1 multiplexer using only elemental logic elements (gates). b. (5 points) Draw the netlist you implement in part a) c. (5 points) Using the 2-to-1 multiplexer module developed in class as a building block, write a Verilog description of the 4-to-1 multiplexer. d. (5 points) Draw the diagram you implement in part c) 2. A decoder sets one output line high and all others low, depending on the input signal. a. (15 points) Write a Verilog description of an 8-bit decoder called
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Unformatted text preview: addr_dec8 using only elemental logic elements or instances (module instantiations). You MUST use the hierarchical design style. b. (5 points) Draw the netlist and/or diagram you implement in a) Hint: You need to create multiple modules and draw a diagram or netlist for each module. in [2] in [1] in [0] out [7] out [6] out [5] out [4] out [3] out [2] out [1] out [0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i0 i1 i2 i3 s0 s1 z out[0] out[7] out[6] out[5] out[4] out[3] out[2] out[1] in[2:0] 3 Truth Table...
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