ece406f08hw3

ece406f08hw3 - NC State University ECE Department ECE 406...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
NC State University ECE 406 Fall 2008 ECE Department Design of Complex Digital Systems Homework #3 Due: 9/17/2008 Submit through wolfware Design Verilog modules according to the following description. NOTE: problems 1 and 2 will be graded using the Verilog simulator in conjunction with test fixtures designed by the instructor. 1. The module name is “extension”. Its input is a 16-bit vector called “ir”. There are 4 outputs described as follows: (20 points) a) “imm5”: sign-extending the last 5 bits of “ir” to 16 bits; b) “offset11”: sign-extending the last 11 bits of “ir” to 16 bits; c) “offset9”: sign-extending the last 9 bits of “ir” to 16 bits; d) “offset6”: sign-extending the last 6 bits of “ir” to 16 bits; You can ONLY use dataflow description, i.e., with the keyword “assign” when describing the functionality of the module. Name your file “hw3.1.v” and submit it through wolfware. 2.
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/30/2009 for the course ECE 406 taught by Professor Davis during the Spring '08 term at N.C. State.

Ask a homework question - tutors are online