NC State University ECE 406 Fall 2008 ECE Department Design of Complex Digital Systems Homework #4 Due: 10/8/2008 Write a complete Verilog module description for the following systems. You must submit your design through wolfware. 1. A Racing light controller. (20 points) Input: Three 1-bit signals called clock , start , and reset , Output: One 3-bit signal called Sout Functional description: The module name is RaceLight. The legal values of Sout are 3’b001, 3’b010, and 3’b100. The input clock is the system clock. The Sout becomes 3’b001 as soon as the input reset turns high. The Sout cannot be changed when reset is high. When reset is low, Sout changes at the positive edge of clock as described in the following state transition graph. When Sout is not equal to any legal values, it always changes to 3’b001 at the next positive edge of clock or reset . Name your file as “hw4.1.v”. 2.
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