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ece406f08hw5 - NC State University ECE Department ECE 406...

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NC State University ECE 406 Fall 2008 ECE Department Design of Complex Digital Systems Homework #5 Due: 10/22/2008 1. You need to complete the Logic Synthesis Tutorial described below. Write a report for the tutorial following the “Lab write-up sample” given on the Lab page of the course web-site. Be sure to answer all questions in the report and include a print-out of your waveforms. The TA whom you show your design to MUST sign on your report (See Q6 in the tutorial) (90 points) 2. Submit the Controller module design as described in the project 1. You need to name it as hw5_2.v. Your submission will be tested using a very simple test fixture. You will earn either 5 points or 0 point depending on whether your code can pass the test or not. The fact that your code passes the simple test does not ensure the correctness of your design, since the simple test does not perform an exhaustive test. You still need to create your own tests to verify your Controller design when you work on Project 1. No solution will be posted for this part of homework. 3. Submit the Fetch module design as described in the project 1. You need to name it as hw5_3.v. Your submission will be tested using a very simple test fixture. You will earn either 5 points or 0 point depending on whether your code can pass the test or not. The fact that your code passes the simple test does not ensure the correctness of your design, since the simple test does not perform an exhaustive test. You still need to create your own tests to verify your Fetch module when you work on Project 1. No solution will be posted for this part of homework. Logic Synthesis Tutorial 1. Introduction The purpose of this tutorial is to let you gain hands-on experience on the automatic conversion of Verilog descriptions to real hardware circuits. There exist many conversion methods. In this tutorial, you will use a software tool called Quartus and a print circuit board called Altera DE2. 2. Learning Objective Learn to convert the Verilog description of a module into a circuit netlist Learn to design with Quartus II CAD system and Altera DE2 board 3. Laboratory Report You are expected to submit a report. Items expected in the report are written as questions (Q) in this documentation. Follow the sample lab when preparing your report.
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NC State University ECE 406 Fall 2008 ECE Department Design of Complex Digital Systems 4. Required Files You need the following files to complete this tutorial: xorlight.v: A simple XOR gate Verilog description as an example to illustrate the design procedure. xorlight.csv: A pin-constraint file to match pins on the Cyclone FPGA to switches and LEDs on the Altera DE2 print circuit board. count.v: A file to demonstrate Quartus deal with timing issues bad.v: A file to illustrate how Quartus identifies and reports common coding errors.
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