hw2_soln - module demux1to2(z0 z1 in s input in s output z0...

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NC State University, Department of Electrical and Computer Engineering ECE 40 6 - Homework #2- Solution 1. A 4-to-1 multiplexer selects one of four input lines to pass through to a single output line. The selection is controlled by a 2-bit control input. s 1 ,s 0 z 0 0 i0 01 i1 10 i2 11 i3 b. Logic Diagra m a. V erilog Module Description module mux_4 (z, i0, i1, i2, i3, s0, s1); input i0, i1, i2, i3, s0, s1; output z; wire s0bar, s1bar; not (s0bar, s0); not (s1bar, s1); and (x0 , i0 , s0bar , s1bar); and (x1 , i1 , s 1 bar , s 0 ); and (x2 , i2 , s 1 , s 0 bar); and (x3, i3, s0, s1); or (z, x0, x1, x2, x3); endmodule d. Logic Diagr am c. V erilog Module Description module mux_4 (z, i0, i1, i2, i3, s0, s1); input i0, i1, i2, i3, s0, s1; output z; wire x, y; mux_2 z1 (x, i0, i1, s1); mux_2 z2 (y, i2, i3, s1); mux_2 z3 (z, x, y, s0); endmodule i0 i1 i2 i3 s0 s1 z i0 i1 i2 i3 s 1 s 0 x0 x1 x2 x3 z s 1 bar s 0 bar i0
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2. First create the gate-level Verilog description and schematic of a 1-to-2 demultiplexer.
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Unformatted text preview: module demux1to2 (z0, z1, in, s); input in, s; output z0, z1; wire n_s; not n1 (n_s, s); and a1 (z0, n_s, in); and a2 (z1, s, in); endmodule The structural description of the 8-bit decoder using only 1-to-2 demuxes is given below. The schematic is given on the following page. module addr_dec8(out, in); output [7:0] out; input [2:0] in; wire x0,x1,y0,y1,y2,y3; demux1to2 u1 (out[0], out[1], y0, in[0]); demux1to2 u2 (out[2], out[3], y1, in[0]); demux1to2 u3 (out[4], out[5], y2, in[0]); demux1to2 u4 (out[6], out[7], y3, in[0]); demux1to2 u5 (y0, y1, x0, in[1]); demux1to2 u6 (y2, y3, x1, in[1]); demux1to2 u7 (x0, x1, 1’b1, in[2]); endmodule // addr_dec8 n_s in s z0 z1...
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This note was uploaded on 03/30/2009 for the course ECE 406 taught by Professor Davis during the Spring '08 term at N.C. State.

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hw2_soln - module demux1to2(z0 z1 in s input in s output z0...

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