ECE 403 Homework 2 Due in class before lecture on Friday, 1/23/09 1)Analytically consider a Common-Drain gain stage with Vdd=5 volts, a passive load R=30kΩ, an n-channel MOSFET drive transistor with W=100 μm, L=2 μm, and ideal low-frequency model with VTO=1 V, KP=100 μA/V2. Draw the circuit (i.e. the real large-signal circuit) and label every node and element appropriately. a)Analytically calculate the dc value of Vin (i.e. the large-signal bias value) to make the operating point have Vout=2.5 V b)Draw the small-signal model for the circuit and label every node and element appropriately. c)Analytically calculate the small signal gain at this operating point. 2)Using PSpice in NCSU Virtual Computing Lab or PSpice on your own PC, Capturethe same C-D circuit using an MBreakn4-terminal nmos element. In the PropertiesEditor, set W=100u and L=2u for the nmos and adjust their display properties to displaythe names and valuesof W and L on the schematic. Use the modeleditorto set model parameters Vto=1 and Kp=100u for the nmos.
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This note was uploaded on 03/30/2009 for the course ECE 403 taught by Professor Bilbro during the Spring '08 term at N.C. State.