TestCircuitSchematic - If all the FETs on an IC were in C-S...

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Here’s the test circuit with ideal voltage sources Vds, Vgs, and Vs applied across the terminals exactly as assumed by the LEVEL=1 current model…In this picture the actual voltage at the gate node is Vg=Vsb+Vgs , and the actual voltage at the drain is Vd=Vs+Vds, but the model is historically formulated in terms of Vds and Vgs instead of just Vd and Vg. Originally Vs=Vb . (Actually this is still true for discrete MOSFETs, like for a RadioShack power MOSFET, which is separately packaged in its own little can with just one FET on its own silicon substrate and just three lead wires.) However for integrated circuits (ICs), it is useful to put many transistors on the same substrate.
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Unformatted text preview: If all the FETs on an IC were in C-S amps, then maybe you could still have all their sources and all their drains all at ground, but that would preclude any C-G or C-D stages anywhere on the chip. Nowadays, there are more modern (and more expensive) processes that can realize electrically isolated wells for any one or any collection of nmosfets (and can do the same for pmosfets), so that each well can act as a substrates for one or many FETs, as needed. Vs Vd Vds Vg Vgs Vb=Vbody =Vbulk=Vbackgate Vs=Vsb M MbreakN L = W =...
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This note was uploaded on 03/30/2009 for the course ECE 403 taught by Professor Bilbro during the Spring '08 term at N.C. State.

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