ENGRD2300: Introduction to Digital Logic
Fall 2008
Homework 2
Due Wednesday, Sept. 17, at 1:25pm
Problem 1.
You need to drive a large number of 74HC00-like inputs with 74HC00 NAND gates. What is
the maximum number of 74HC00-like inputs that you can connect to one single 74HC00 output without
exceeding its worst-case loading specifications (fanout)? Use Wakerly Table 3-3.
Hint: Calculate BOTH
LOW-state and HIGH-state DC fanouts.
Problem 2.
Wakerly Drill Problems 3.27 (b), (d), (f) and (g)
Problem 3.
You are given an inverter driving a 50 pF capacitive load. When the inverter input
changes from high to low, the circuit looks as follows:
a) What is the output voltage as a function of time?
b) Assuming that at time t = 0, V
OUT
is 0.0V, at what time will the value of V

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