hw7 - ENGRD2300: Introduction to Digital Logic Fall 2008...

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Fall 2008 Homework 7 Due Wednesday, Nov 19, at 1:25pm Problem 1. Calculate the MTBF of a synchronizer built according to Wakerly Figure 8-76 using (a) 74LS74, (b)74ALS74 and (c) 74F74 flip-flops, assuming a clock frequency of 25MHz and an asynchronous transition rate of 1MHz. Assume that the set-up time of the 74LS74 is 20ns, the 74ALS74 is 10ns and the 74F74 is 5ns. Assume that the hold time for each type of flip-flop is 0ns. Which flip-flop gives you the most job security? Why? Problem 2. In the style of Wakerly Figure 9-9, describe a possible layout of a 64K x 4 ROM. Remember we like “square” chips! Problem 3. a) Show how, using additional SSI/MSI parts, a 2764 8K x 8 ROM can be used as a 64K x 1 ROM. CS_L A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 b) Show how, using additional SSI/MSI parts as necessary, eight 64K x 1 ROMs can be used as a 64K x 8 ROM. 1
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This note was uploaded on 03/31/2009 for the course ECE 230 taught by Professor Long during the Fall '08 term at Cornell University (Engineering School).

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hw7 - ENGRD2300: Introduction to Digital Logic Fall 2008...

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