lab4 - ENGRD 230: Introduction to Digital Logic Design Lab...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Fall 2008 Lab 4: Arithmetic Logic Unit Lab 4. Designing an Arithmetic Logic Unit In this lab you will design, build, and test an Arithmetic Logic Unit (ALU). The prelab for this lab is to be turned in no later than 1:25pm, Saturday, Oct 4, 2008. The Lab portion is to be completed either during your lab section the week of Oct 6, 2008. Your final lab report is due right after Fall Break, Wed. Oct. 15 at 1:25pm. Part I: Prelab For this lab you may work with a partner on the prelab. If you choose to do so, you should choose a partner from your lab section so that you can work with the same person in lab. You will also have to turn in your prelab as a group in CMS. For this lab you will design and test an Arithmetic Logic Unit, or ALU, that performs a set of specified arithmetic and logical functions. Your design will be downloaded into the Cyclone II EP2C35F672C6 FPGA on the Altera DE2 development boards. (The PB-503 Proto-Board systems will not be used for this, or for any other lab for the rest of this semester.) You will draw your circuit using Quartus II using standard 7400 series ICs and then the software will create this design in the FPGA. This design will take longer than you expect; please start the prelab early. Your design will be graded on its overall functionality; therefore you should primarily concentrate on creating a design that works. However, you should pay some attention to creating an efficient design as an overly inefficient design would be more expensive to manufacture. You must have your design ready for implementation during your lab period. Make sure you bring a flash drive with your Quartus II files, place them onto your ECE Z: drive or have them on a machine that can be reached via FTP. Also bring paper copies of your circuit diagrams, timing diagrams, floor plans, and any other support work as you will no doubt need to make some changes during the lab. For your convenience, a set of template files for this lab has been placed on Blackboard for you to download. The top-level design file is called lab4.bdf and contains all the inputs and outputs that you will need for this lab. It also contains a block for your ALU. You will not need to make any changes to lab4.bdf. You should use the alu.bdf design file for your ALU design. This template file defines only the required inputs and outputs; you will have to provide the remaining design elements. The template files also contain a seven segment display driver, seven_seg.v that is used to drive two seven segment displays on the DE2 board with the output of your ALU. The block symbol for the ALU is given below. It is an 8-bit functional unit capable of performing any of the eight operations described below. There will be two data inputs, A and B, each eight bits wide, as well as an output Y of the same width. The CI input is used for Carry In. The CO, OVR, NEG, and ZRO outputs are the Carry Out, Overflow, Negative, and Zero outputs, which should be asserted if any of those conditions arise on the output bus Y. 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/31/2009 for the course ECE 230 taught by Professor Long during the Fall '08 term at Cornell University (Engineering School).

Page1 / 8

lab4 - ENGRD 230: Introduction to Digital Logic Design Lab...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online