ASU_eee230_Assignment 6

# ASU_eee230_Assignment 6 - Alejandro A. Tinoco Dr. Debra...

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Alejandro A. Tinoco Dr. Debra Calliss CSE/EEE 230 Fall 2007 Assignment 6 April 1, 2008 1. Consider the code below: add \$3, \$5, \$6 add \$5, \$5, \$1 sub \$2, \$3, \$1 add \$4, \$5, \$2 sub \$4, \$4, \$1 a. Draw the pipeline diagram similar to Figure 6.5 for this code if NO forwarding is done. b. How many clock cycles does this code take without forwarding? - 14 clock cycles

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c. Using a drawing similar to Figure 6.5, show the forwarding paths needed to execute the above code. d. How many clock cycles does this code take with forwarding? - 9 clock cycles e. At cycle 5, determine the values of the 4 pipeline registers if each register has an initial value of its number. Do not include the control in your answer. IF/ID ID/EX EX/MEM MEM/WB Sub \$4, \$4, \$1 Op = add \$2 = 10 \$5= 6 rs = \$5 rt = \$2 rd = \$4 2. Consider the code below: add \$2, \$3, \$1 #1 add \$4, \$3, \$4 #2 sub \$3, \$2, \$1 #3 lw \$4, (\$6) #4 add \$2, \$4, \$1 #5
a. Identify all the data dependencies in the code. Which of these hazards can be resolved by forwarding and which must be resolved by stalling? -

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## This note was uploaded on 04/06/2009 for the course CSE CSE/EEE230 taught by Professor Debracaliss during the Fall '09 term at ASU.

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ASU_eee230_Assignment 6 - Alejandro A. Tinoco Dr. Debra...

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