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Unformatted text preview: Prelab 8: Multi-stage Ampliﬁers
Name: Lab Section: VCC = 5 V ISUP P LY vOUT Q2 VBIAS 2 + − − VBIAS 1 + − vin + RS Q1 Figure 1: Cascode ampliﬁer with ideal current source 1. The cascode in Figure 1 is biased by an ideal current source. Let RS = 51 Ω, IS = 1 × 10−15 A, VA = 100 V, β = 200, ISUP P LY = 1 mA, T = 300 K, vOUT,DC = 3.5 V, and VBIAS 2 = 2 V. Calculate the value of VBIAS 1 that corresponds to these biasing conditions. VBIAS 1 = 2. What is the gain of this ampliﬁer? Av = 1 2 VCC = 5 V RC IBIAS 1 vOUT 1 + vIN − RS Q1 vOUT 2 Q3 Q4 Q2 RREF IBIAS 2 Figure 2: Multi-stage ampliﬁer 3. Now construct a SPICE netlist for the multi-stage ampliﬁer shown in Figure 2. Let RC = 10 kΩ, RS = 51 Ω, and RREF = 200 Ω. Bias transistor Q1 with VIN = 560 mV. What is the small signal gain (Av1 ) between vIN and vOUT 1 ? What is the small signal gain (Av2 ) between vOUT 1 and vOUT 2 ? Using Av1 and Av2 , ﬁnd the overall gain (Av,tot ) between vIN and vOUT 2 . Attach the SPICE netlist to the end of this prelab. Hint: When making your netlist, recall the notation: vIN = vin + VIN . Av1 = Av2 = Av,tot = 4. Using the same setup from the previous question, simply change VIN to 610 mV and rerun the test. What are the new values for Av1 , Av2 , and Av,tot ? From your results, does DC biasing have a profound eﬀect on the small signal gain? Explain. Av1 = Av2 = Av,tot = ...
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- Spring '08