EE357 Lecture 3

EE357 Lecture 3 - Recap: M68000 ISA CISC style 32-bit...

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EE 357 Lecture 3 RTL Operations & Instructions Operands & Addressing Modes Recap: M68000 ISA CISC style 32-bit internal / 16-bit external data size Registers and ALU are 32-bits wide Supports subsizes: 8-bits (Byte), 16-bits (Word), 32-bits (Longword) Memory data bus is 16-bits wide Can perform 32-bit reads and writes by doing 2 16-bit reads or writes Memory address bus is 24-bits wide (max. 2 24 = 16 MB mem.) Separate data and address registers 8 data registers (D0-D7) 8 address registers (A0-A7) 1 word (16-bit) instruction with 1-4 extension words stored after the instruction word Recap:M68000 Processor M68000 PC: IR: D0±-D7 A0±-A7 ALU 32 32 32 Control 32 32 Data Registers – Hold data operands Address Registers – Act like pointers to data in memory Special Registers – PC: Program Counter (24- bits) • Holds the address of the next instruction to be executed – IR: Instruction Reg. (16-bits) • Holds the current instruction as it executes – SR: Status Reg. (16-bits) • Holds control bits and state of the processor Data & Address Registers (General-Purpose) Special Registers SR: Recap: M68000 Data Sizes • 3 Sizes Defined –Byte (.B) •8 -b i ts – Word (.W) • 16-bits = 2 bytes – Longword (.L) • 32-bits = 4 bytes
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Recap: Registers & Data Size • Instructions specify what size of data to operate on – ADD.B –MOVE .W – ADD.L • Register sizes are right-justified (start at LSB and work left) 31 0 Byte operations only access bits 7-0 of a register (upper bits are left alone) Byte 7 31 0 Word operations only access bits 15-0 of a register (upper bits are left alone) Word 31 0 Longword operations use the entire 32-bit value Longword 15 Dx: Ax/Dx: Ax/Dx: • M68000 smallest accessible unit is a byte so we still have one address for every byte • 16-bit data bus allows us to access 2-bytes of data at a time • Conceive of memory being arranged in rows of 2-bytes – Separate addresses for each byte • Think of the memory as being arranged in word-size rows (i.e. 2-byte rows) 5A 000000 13 F8 7C 29 33 000001 000002 000003 000004 000005 Recap: M68000 Memory 5A 13 F8 7C 29 33 000000 000002 000004 Original Byte-Oriented View M68000 Word-Oriented View Recap: Memory & Data Size Byte operations only access the byte at the specified address N N+1 N+2 N+3 (Assume start address = N) Word operations access the 2-bytes starting at the specified address N N+1 N+2 N+3 Longword operations access the 4-bytes starting at the specified address N N+1 N+2 N+3 Same 3 sizes defined for memory – Byte (.B) = 1 byte – Word (.W) = 2 bytes – Longword (.L) = 4 bytes Always provide the starting starting address & size Memory is left justified (start at MSB and work right) Memory Access Rules – Word or Longword access must start on even address (i.e. an entire row) • How does it work? – Supply the starting address of the byte, word, or longword – Indicate the size – The memory takes care of the rest Recap: 68000 Memory Access 5A 13 F8 7C 29 33 000000 000002 000004 Addr Data Control
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• Valid words and longwords only allowed to start on EVEN addresses: – Word @ 0 – good (even) – Word @ FFE6 – good
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This note was uploaded on 04/11/2009 for the course EE 357 taught by Professor Mayeda during the Fall '08 term at USC.

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EE357 Lecture 3 - Recap: M68000 ISA CISC style 32-bit...

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