EE357Lecture11-4

EE357Lecture11-4 - Exceptions Any event that causes a break in normal execution EE 357 Lecture 11 Exceptions Memory System Organization Error

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EE 357 Lecture 11 Exceptions Memory System Organization Exceptions • Any event that causes a break in normal execution – Error Conditions • DIV by 0, odd address used for .W/.L access, etc. – Hardware Interrupts / Events • Handling a keyboard press, mouse moving, new USB device, etc. • Will be discussed later in the semester – System Calls / Traps • User applications calling OS code Error Condition Exceptions • Bus Error – No memory or I/O device responds to a read or write • Address Error – Odd address used for W/L access • Illegal instruction – Invalid opcode • Zero Divide • CHK instruction • TRAPV (Trap on Overflow) – An instruction that can call a handler routine if the V flag = 1 • Privilege violation – User code attempting to perform supervisor mode operation Supervisor and User Mode • User applications are designed to run in user mode • Operating System and other system software should run in supervisor mode • Certain features/privileges are only allowed to code running in supervisor mode
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System Calls / TRAPs • Provide an entry point for user mode applications to call supervisor mode (OS) code • TRAP’s are very similar to subroutine calls but they switch into supervisor mode when called and then back to user mode on return Exception Handling • What do we do when an exception occurs? – A routine called an “exception handler” will be automatically called to attempt to handle the exception • Problems with calling exception handlers – We don’t know where we will be in our code when an exception occurs, so how can we call the exception handler – Calling the exception handler can cause changes in state when we return to running application Problem of Calling a Handler • We can’t use explicit BSR/JSR instructions to call exception handlers since we don’t when they will occur ORG $1000 MAIN ---- ---- ---- ---- ---- STOP #$2700 Many instructions could cause an error condition. Or a hardware event like a keyboard press could occur at any point in the code. EVT • EVT is a reserved area in memory defined from address $0 - $3FF – 256 32-bit addresses – Vector 1 : starting stack address – Vector 2 : starting code address – 3-15 : Errors – 25-31 : Interrupts – 32-47 : TRAP instruction vector • Specific entries for each exception • Each long-word entry should be filled in with the starting address of the exception handler associated with that exception Init. SP Init. PC Illegal Inst. Divide by 0 CHK instruc. 0 4 8 C 10 14 18 1C TRAPV Privilege Viol. ... INT1 20 64 7C ... INT7 TRAP0 80 BC ... TRAP15 Bus Error Address Error EVT ... 3FF
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Follow Along Exercise on Traps 0000 0000 0000 0000 0000 0000 0000 TRAP 0 TRAP 1 TRAP 2 80 84 88 8C Exception Vector Table MOVE.L #T1,$84 ...
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This note was uploaded on 04/11/2009 for the course EE 357 taught by Professor Mayeda during the Fall '08 term at USC.

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EE357Lecture11-4 - Exceptions Any event that causes a break in normal execution EE 357 Lecture 11 Exceptions Memory System Organization Error

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