EE357Lecture20-4

EE357Lecture20-4 - Concepts & Skills Concepts A simple...

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E 357 Lecture 20 EE 357 Lecture 20 3-Bus Multi-Cycle CPU Organization oncepts & Skills Concepts & Skills oncepts Concepts – A simple hardware organization can implement M68000 instructions – Assertion of control signals (output, input enables, etc.) at the appropriate time to fetch, decode, and xecute an instruction execute an instruction. • Skills iven an instruction produce the appropriate control Given an instruction, produce the appropriate control sequence • Just memorize the Fetch and Decode phase steps • For the execution phase, remember to fetch extension words PU Organization CPU Organization ulti- ycle CPU Architecture Multi Cycle CPU Architecture – Multiple cycles to execute each instruction hree us Architecture – Three-Bus Architecture • Registers (Data and Address Registers) – Output enables p – Input enables •ALU • Memory access – MAR (Memory Address Register) DR (Memory Data Register) MDR (Memory Data Register) PU Architecture CPU Architecture he most basic thing we need to specify in The most basic thing we need to specify in building a CPU is how the parts will communicate with each other – how do we get values from registers to the ALU – how do we get results from the ALU back to the registers –e tc . ince the ALU requires 2 inputs and 1 output we • Since the ALU requires 2 inputs and 1 output we will begin by studying the Three-Bus rchitecture Architecture
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hree- us CPU Three Bus CPU hown here are the D0 Shown here are the registers and the ALU •T h ey need to D7 A0 y communicate with each other to do A7 C MOVE’s, ADD’s, etc. PC IR A L U A B F hree- us CPU Three Bus CPU • To communicate between D0 the registers and ALU we will use 1 bus for each LU input and a bus for D7 A0 ALU input and a bus for the ALU output • These buses are different A7 C than the external address or data bus that is used to ccess memory they are PC IR 32 32 32 access memory…they are internal buses to allow the registers and ALU to it A L U A B F communicate Bus C Bus A Bus B hree- us CPU Three Bus CPU egisters should D0 inputs to registers outputs of registers Registers should output to either bus A or B and receive input D7 A0 from C • ALU is the opposite A7 C • Ex.: ADD.W D0,D1 – In this case, we’d want PC IR output of LU inputs to LU 32 to output D0 and D1 onto bus A and B respectively and then ALU ALU A L U A B F py clock in the result to D1 from Bus C Bus C 32 Bus A Bus B 32 hree- us CPU Three Bus CPU Problems with D0 inputs to registers outputs of registers Three-Bus structure 1. All outputs share oth bus A and D7 A0 both bus A and B…bus contention 2. All inputs are A7 C attached to one bus…we don’t want all registers clocking PC IR output of LU inputs to LU 32 in the same value Solution: Control the utputs and inputs of ALU ALU A L U A B F outputs and inputs of the registers Bus C 32 Bus A 32
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utput Enables Output Enables DQ D0[0] bit 0 bit 31
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EE357Lecture20-4 - Concepts & Skills Concepts A simple...

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