State University of New York at Stony Brook
Department of Electrical and Computer Engineering
ESE 218 Digital Systems Design
Spring 2009
Lab 3. Twolevel implementations
1. Objectives
De
sign
of
2to1 data selectors implementing SOP and POS algebraic expressions.
A
naly
sis of
the circuits for possibility and specifics of glitches. Glitchfree design.
2. Introduction
Designing combinational circuits we have to ensure that the circuit operates properly for
all possible input combinations.
Some combinations can be hazardous causing unwanted
glitches that appear at the output due to different propagation delays on different paths
though the circuit. Glitch is an unexpected shorttime change in the output value. The
concept of glitchfree design will be illustrated on the example of data selectors or
multiplexers widely used in digital systems. The circuit you are going to design allows
propagation of signal from input A to output F with control signal C =1 and propagation
of signal B to the output with C = 0. One of the possible implementations is shown in
Figure 1.
Figure 1.
3. Prelab
1.
Obtain the algebraic expression for output F for the circuit in Figure 1 in the sum
ofproducts (SOP) form. Draw the circuit diagram for NAND–NAND
implementation of the expression. Assuming the same propagation delay of 10 ns
for all gates, obtain the timing diagram for output F when the data inputs are both
at logical 1 level and the control input value changes from 0 to 1 then, after 50 ns,
A
B
C
F
Control
input
Data
inputs
F2
F1
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document2
changes back from 1 to 0. To do that first draw the timing diagrams for
This is the end of the preview.
Sign up
to
access the rest of the document.
 Spring '08
 DONETSKY
 TA, Logic gate, The Circuit, Circuit diagram

Click to edit the document details