lab5 - State University of New York at Stony Brook...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
1 State University of New York at Stony Brook Department of Electrical and Computer Engineering ESE 218 Digital Systems Design Spring 2 00 9 Lab 5 . Binary adder/subtractor 1. Objectives a). De sign of the binary adder/subtractor operating with 5-bit signed binary numbers. Negative numbers are to be presented in the 2’s complement form. The design should detect overflow. b). Comparison of the propagation delays for the ripple-carry and carry-lookahead designs. The circuit diagram for the ripple-carry adder (iterative network) ha s to be specified in PSPICE using hierarchical approach. 2. Introduction The ripple carry adder can be classified as an iterative network. The feature common to the iterative networks is that multiple "one bit slices" of the network can be cascaded to perform the required operation on multiple bits. For example, the 1-bit full adder is a 1-bit slice of the multiple-bit ripple carry adder. The easiest way to design the iterative network is to identify the recurrent relationships between the successive bits in a sequence. For the ripple carry adder one cell in the iterative network is defined by the following equations: S i = A i B i Ci and C i+1 = A i B i + C i (A i B i ), where C i is the carry-in from a predecessor and C i+1 is the carry-out to a successor. The major drawback of the ripple-carry designs is their poor speed. One has to wait for the carry to ripple through all the cascades before the output carry (indicating validity of the addition) become available. Therefore for the ripple carry circuit the worst-case propagation delay corresponds to propagation of the carry signal and the propagation delay is proportional to the number of digits. With the carry-lookahead approach and at the expense of complexity this delay can be reduced to a fixed value independent o f the number of digits. Using notation P i = A i B i for carry - propagates and G i = A i B i for carry - generates, the equation for the carry-out above will have the form C i+1 = G i +P i C i . For example, for the second bit ( i =1) the carry-out can be presented as C 2 = G 1 +P 1 (G 0 + P 0 C 0 ) = G 1 +P 1 G 0 + P 1 P 0 C 0 (1) Implementation of the left part of equation (1) with a 4-level circuit reflects the ripple-carry principle: C 1 (= G 0 + P 0 C 0 ) is obtained first, then C 2 is obtained by iteration. In contrast, the right part of the equation with distributed term P 1 reflects the carry-lookahead principle. The
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/12/2009 for the course ESE 218 taught by Professor Donetsky during the Spring '08 term at SUNY Stony Brook.

Page1 / 4

lab5 - State University of New York at Stony Brook...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online