lab6 - State University of New York at Stony Brook...

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1 State University of New York at Stony Brook Department of Electrical and Computer Engineering ESE 218 Digital Systems Design Spring 2009 Lab 6. Decoders 1. Objectives a). Design a 3-to-8 binary decoder with active-low outputs. Implement binary functions RD, AC and WR using the decoder and additional gates: RD (A,B,C) = (0, 1, 2, 3, 4) AC (A,B,C) = (5, 6) WR ( A,B,C) = m 7 b) Write a gate-level description of the circuit in Verilog, identify the critical path, obtain the timing diagram for the critical path using SynaptiCAD 1 and determine the propagation delay. 2. Introduction Decoders are used in all digital systems: for example, memory chips have to decode binary address to access a particular cell; microprocessors have to decode instructions. The instructions include the operation code (Opcode) and references to operand locations – registers inside the microprocessor or external memory. Suppose Arithmetic and Logic Unit (ALU) of your microprocessor can perform 8 different operations to be selected by a 3-bit code. Besides selection of a particular operation, the instruction decoder generates signals RD, AC, WR to control data flow between the registers. Assume Opcodes 0 through 4 are reserved for the following arithmetic and logic operations with two operands: ADD, SUBTRACT, bit-by-bit AND, OR and XOR. One of the operands is located in a special register – accumulator A; and the result of the operation is to be stored in the accumulator: A A + R. To perform these operations, the decoder generates signal RD that takes control on reading the second operand from register R and storing the result in accumulator A. Opcodes 5 and 6 are reserved for complement (A NOT A) and increment (A A+1) of the accumulator contents with keeping the result in the accumulator. The decoder generates signal AC to control dataflow during these operations. Opcode 7 (
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lab6 - State University of New York at Stony Brook...

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