l07_caches - 1 Multilevel Memories Joel Emer Computer...

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1 Multilevel Memories Joel Emer Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Based on the material prepared by Krste Asanovic and Arvind
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6.823 L7- 2 Joel Emer CPU-Memory Bottleneck Memory CPU Performance of high-speed computers is usually limited by memory bandwidth & latency • Latency (time for a single access) Memory access time >> Processor cycle time • Bandwidth (number of accesses per unit time) if fraction m of instructions access memory, 1+ m memory references / instruction CPI = 1 requires 1+ m memory refs / cycle October 3, 2005
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6.823 L7- 3 Joel Emer Core Memory Core memory was first large scale reliable main memory – invented by Forrester in late 40s at MIT for Whirlwind project Bits stored as magnetization polarity on small ferrite cores threaded onto 2 dimensional grid of wires Coincident current pulses on X and Y wires would write cell and also sense original state (destructive reads) Robust, non-volatile storage Used on space shuttle computers until recently Image removed due to Cores threaded onto wires by copyright restrictions. hand (25 billion a year at peak production) Core access time ~ 1 µ s DEC PDP-8/E Board, 4K words x 12 bits, (1968) October 3, 2005
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6.823 L7- 4 Joel Emer Semiconductor Memory, DRAM Semiconductor memory began to be competitive in early 1970s Intel formed to exploit market for semiconductor memory First commercial DRAM was Intel 1103 1Kbit of storage on single chip charge on a capacitor used to hold value Semiconductor memory quickly replaced core in 1970s October 3, 2005
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6.823 L7- 5 One Transistor Dynamic RAM Joel Emer TiN top electrode (V REF ) 1-T DRAM Cell Ta 2 O 5 dielectric word Image removed due to copyright restrictions. access FET bit Explicit storage poly W bottom TiN/Ta2O5/W Capacitor capacitor (FET word electrode gate, trench, line access fet stack) October 3, 2005
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6.823 L7- 6 Joel Emer Processor-DRAM Gap (latency) µProc 60%/year DRAM 7%/year 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance “Moore’s Law” [From David Patterson, UC Berkeley] Time Four-issue superscalar could execute 800 instructions during cache miss! October 3, 2005
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6.823 L7- 7 Joel Emer Little’s Law Throughput (T) = Number in Flight (N) / Latency (L) Memory CPU Misses in flight table Example: --- Assume infinite bandwidth memory --- 100 cycles / memory reference --- 1 + 0.2 memory references / instruction Table size = 1.2 * 100 = 120 entries 120 independent memory operations in flight! October 3, 2005
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6.823 L7- 8 Joel Emer DRAM Architecture bit lines Col.
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This note was uploaded on 04/14/2009 for the course CS 510 taught by Professor Jaeyukhuh during the Spring '09 term at Korea Advanced Institute of Science and Technology.

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l07_caches - 1 Multilevel Memories Joel Emer Computer...

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