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Unformatted text preview: lead to minimal delay? 3. Consider the circuit as shown in Fig. 1. The gate capacitance of the unit sized inverter ( n = p ) is C g . Suppose C L = 64 C g and the capacitance of the wire can be ignored. The delay from A to B is denoted by t d . Under the same supply voltage V DD , for three different values of a : a 1 = 1 , a 2 = 2 , and a 3 = 6 , the circuit will have three values of t d : t (1) d , t (2) d , and t (3) d . Calculate the ratio t (1) d : t (2) d : t (3) d . (Ignore the wire resistance and capacitance.) a 1 a 2 a 3 A B C L Figure 1: 4-cascaded inverters with stage ratio a. 1...
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- Spring '08