# HWK2 - lead to minimal delay 3 Consider the circuit as...

This preview shows page 1. Sign up to view the full content.

ECSE 4220 VLSI Design Homework #2 Due: Feb. 15 in class 1. Design an complementary static CMOS circuit with minimized number of transistors to realize the Boolean function: F=A’B’+C’A’, and assign the relative size to each transistor in such a way that (1) charge time and discharge time are equal, and (2) charge time is one half of discharge time. (Suppose μ n = 2 μ p ). 2. Consider the wire represented as distributed RC sections. The total wire length is 3mm. To reduce the wire delay, we evenly insert n buffers along the wire. Suppose r=10 Ohms/micron and c = 0.2 fF/micron and the delay of each buffer is 1ns. What is the value of n that could
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: lead to minimal delay? 3. Consider the circuit as shown in Fig. 1. The gate capacitance of the unit sized inverter ( β n = β p ) is C g . Suppose C L = 64 C g and the capacitance of the wire can be ignored. The delay from A to B is denoted by t d . Under the same supply voltage V DD , for three different values of a : a 1 = 1 , a 2 = 2 , and a 3 = 6 , the circuit will have three values of t d : t (1) d , t (2) d , and t (3) d . Calculate the ratio t (1) d : t (2) d : t (3) d . (Ignore the wire resistance and capacitance.) a 1 a 2 a 3 A B C L Figure 1: 4-cascaded inverters with stage ratio a. 1...
View Full Document

## This note was uploaded on 04/14/2009 for the course ECSE 4220 taught by Professor Mcdonald during the Spring '08 term at Rensselaer Polytechnic Institute.

Ask a homework question - tutors are online