hwk4 - connected to GND. Calculate the voltage drop on V o...

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ECSE 4220 VLSI Design Homework #4 Due: April 12 in class 1. Analyze the circuit as shown in Figure 1 and explain its functionality. Figure 1: 2. Consider the circuit as shown in Figure 2, assume that all inputs are initially 0 during the precharge phase and all the internal nodes are initially 0V. Suppose all the nMOS transistors have the same V tn 0 = 0 . 5 V. Ignore the boday effect and calculate the voltage drop on V o , if: (a) Only A changes to 1 (VDD=2V) during the evaluate phase. (b) Both A and B change to 1 (VDD=2V) during the evaluate phase. A B C Clk 50fF 10fF 15fF V o Figure 2: . 1
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3. Re-do the above problem while taking into account of body effect. Assume V tn 0 = 0 . 5 V, 2 φ F =-0.6V, γ = 0 . 4 V 1 / 2 , and the body (i.e., the fourth terminal) of each nMOS transistor is
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Unformatted text preview: connected to GND. Calculate the voltage drop on V o , if: (a) Only A changes to 1 (VDD=2V) during the evaluate phase. (b) Both A and B change to 1 (VDD=2V) during the evaluate phase. 4. Design a dynamic logic circuit with ve inputs: A, B, C, D, and E, and two outputs: F1 = (AB+CD) and F2=(F1+E) . You may choose whatever style you like (e.g., domino, differ-ential domino, zipper . ..) 5. Design a 1-bit full adder using differential domino structure. Minimize the number of tran-sistors (you may want to try the binary dicision diagram (BDD) approach to see whether it can reduce the number of transistors). 6. Problems 6.26 and 6.37 in the textbook. 2...
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This note was uploaded on 04/14/2009 for the course ECSE 4220 taught by Professor Mcdonald during the Spring '08 term at Rensselaer Polytechnic Institute.

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hwk4 - connected to GND. Calculate the voltage drop on V o...

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