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Unformatted text preview: connected to GND. Calculate the voltage drop on V o , if: (a) Only A changes to 1 (VDD=2V) during the evaluate phase. (b) Both A and B change to 1 (VDD=2V) during the evaluate phase. 4. Design a dynamic logic circuit with ﬁve inputs: A, B, C, D, and E, and two outputs: F1 = (AB+CD) and F2=(F1+E) . You may choose whatever style you like (e.g., domino, differential domino, zipper . ..) 5. Design a 1bit full adder using differential domino structure. Minimize the number of transistors (you may want to try the binary dicision diagram (BDD) approach to see whether it can reduce the number of transistors). 6. Problems 6.26 and 6.37 in the textbook. 2...
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 Spring '08
 McDonald
 Voltage drop, evaluate phase, VLSI Design Homework

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