hw4 - HOMEWORK #4 ECE 475/CS 416 Computer Architecture Due...

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HOMEWORK #4 ECE 475/CS 416 – Computer Architecture Due Friday, November 17 at 5pm EST Problem HW4.1 [30 points] Consider a two-issue superscalar implementation of Tomasulo’s algorithm. The processor has enough ALUs (latency 1 cycle) and FPUs (latency 3 cycles) to avoid structural hazards at these. Memory accesses are non-pipelined, i.e., loads and stores are blocking (see below for memory latency). Up to two instructions of any type can be issued every clock cycle. Branch prediction is perfect and there is no delay slot. The code resides in the instruction cache wholly, but the data cache (infinitely large and fully associative, 16B blocks, 1 cycle hit time, 4 cycles miss penalty) is initially empty. Only one CDB is available. When dealing with structural hazards, the oldest instruction has preference (but it cannot preempt any instruction already using the resource). Loads can be reordered dynamically when it is known that they do not overlap in memory with earlier stores. We execute the following loop: LOOP: fld f2,0($1) fmult f4,f2,f0
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This homework help was uploaded on 10/17/2007 for the course COM S 482 taught by Professor Wexler during the Spring '06 term at Cornell.

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hw4 - HOMEWORK #4 ECE 475/CS 416 Computer Architecture Due...

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