Scratchpad Memory A Design Alternative for Cache On-chip memory in Embedded Systems - Scratchpad Memory A Design Alternative for Cache On-chip memory in

Scratchpad Memory A Design Alternative for Cache On-chip memory in Embedded Systems

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Scratchpad Memory : A Design Alternative for Cache On-chip memory in Embedded Systems Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel banakar i mbala~cse.iitd.ernet.in Indian Institute of Technology, Delhi 110 016 steinke I lee { marwedel~lsl2.cs.uni-dortmund.de University of Dortmund, Dept. of Computer Science 44221 Dortmund, Germany ABSTRACT In this paper we address the problem of on-chip mem- ory selection for computationally intensive applications, by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache sizes are computed using the CACTI tool while performance was evaluated using the trace results of the simulator. The tar- get processor chosen for evaluation was AT91M40400. The results clearly establish scratehpad memory as a low power alternative in most situations with an average energy re- duction of J0%. Further the average area-time reduction for the seratchpad memory was 46% of the cache memory. 1 1. Introduction The salient feature of portable devices is light weight and low power consumption. Applications in multimedia, video processing, speech processing, DSP applications and wire- less communication require efficient memory design since on chip memory- occupies more than 50% of the total chip area [1]. This will typically reduce the energy consumption of the memory unit, because less area implies reduction in the total switched capacitance. On chip caches using static RAM consume power in the range of 25% to ,~5% of the total chip power [2]. Recently, interest has been fo- cussed on having on chip scratch pad memory to reduce the power and improve performance. On the other hand, they can replace caches only if they axe supported by an effec- tive compiler. Current embedded processors particularly in the area of multimedia applications and graphic controllers ZThis project is supported under DST-DAAD grants project number MCS 216 Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or COlnmercialadvantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. CODES'02. May 6-8, 2002, Estes Park, Colorado, USA. Copyright 2002 ACM 1-58113-542-4/02/0005...$5.00. have on-chip scratch pad memories. In cache memory sys- tems, the mapping of program elements is done during run- time, whereas in scratch pad memory systems this is done either by the user or automatically by the compiler using suitable algorithm. Although prior studies into scratch pad memory behav- ior for embedded systems have been conducted, the im- pact on area have not been addressed. This paper com- pares cache/scratch pad area models along with their en- ergy models. Specifically we address the following issues I. To support comparison of memory systems we gen- erate area models for different cache and scratchpad

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