hw5soln

hw5soln - ECE 152A Fall 2006 11/14/2006 University of...

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ECE 152A – Fall 2006 11/14/2006 Homework #5 Solution – Page 1 of 20 University of California, Santa Barbara Department of Electrical and Computer Engineering ECE 152A – Digital Design Principles Homework #5 – Solution Problem #1. For the logic diagram below, complete the timing diagram. You can assume the gate delays are much shorter than the clock period. Is this a Mealy machine or a Moore machine and why?
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ECE 152A – Fall 2006 11/14/2006 Homework #5 Solution – Page 2 of 20
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ECE 152A – Fall 2006 11/14/2006 Homework #5 Solution – Page 3 of 20 Problem #2. For the network shown below: 1. Construct a timing diagram for the input sequence: X = 0 1 0 1 0 1 1 1 0 Assume that: 1) X, A and B are all initially equal to 0 2) All transitions of the input X occur on the rising edge of the clock 3) gate delays are much shorter than the clock period. Include all inputs (CLK, X) state variables (A, B) and outputs (Z) in your timing diagram.
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11/14/2006 Homework #5 Solution – Page 4 of 20 2. Construct next state maps for the network.
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hw5soln - ECE 152A Fall 2006 11/14/2006 University of...

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