CMOS Design Rules - TABLE2.2CMOSprocesslayers Mask/layer...

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TABLE 2.2 CMOS process layers. Mask/layer name Derivation from drawn layers Alternative names for mask/layer MOSIS mask label n -well = nwell   1 bulk, substrate, tub, n -tub, moat CWN p -well = pwell  1 bulk, substrate, tub, p -tub, moat CWP active = pdiff + ndiff thin oxide, thinox, island, gate oxide CAA polysilicon = poly poly, gate CPG n -diffusion implant   2 = grow (ndiff) ndiff, n -select, nplus, n+ CSN p -diffusion implant  2 = grow (pdiff) pdiff, p -select, pplus, p+ CSP contact = contact contact cut, poly contact, diffusion contact CCP and CCA   3 metal1 = m1 first-level metal CMF metal2 = m2 second-level metal CMS via2 = via2 metal2/metal3 via, m2/m3 via CVS metal3 = m3 third-level metal CMT glass = glass passivation, overglass, pad COG CMOS Design Rules Figure 2.11 defines the  design rules  for a CMOS process using pictures. Arrows between objects denote a minimum spacing, and arrows showing the size of an object denote a  minimum width. Rule 3.1, for example, is the minimum width of poly (2   ). Each of the  rule numbers may have different values for different manufacturers—there are no  standards for design rules. Tables 2.7–2.9 show the MOSIS scalable CMOS rules.  Table 2.7 shows the layer rules for the  process front end
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  • Fall '15
  • prasad
  • Tour de Georgia, Mac OS X, Surround sound, Passivation, minimum space

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