Faults - Faults Fabrication of an ASIC is a complicated...

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Faults Fabrication of an ASIC is a complicated process requiring hundreds of processing steps. Problems may introduce a defect that in turn may introduce a fault (Sabnis [ 1990] describes defect mechanisms ). Any problem during fabrication may prevent a transistor from working and may break or join interconnections. Two common types of defects occur in metallization [ Rao, 1993]: either underetching the metal (a problem between long, closely spaced lines), which results in a bridge or short circuit ( shorts ) between adjacent lines, or overetching the metal and causing breaks or open circuits ( opens ). Defects may also arise after chip fabrication is complete— while testing the wafer, cutting the die from the wafer, or mounting the die in a package. Wafer probing, wafer saw, die attach, wire bonding, and the intermediate handling steps each have their own defect and failure mechanisms. Many different materials are involved in the packaging process that have different mechanical, electrical, and thermal properties, and these differences can cause defects due to corrosion, stress, adhesion failure, cracking, and peeling. Yield loss also occurs from human error—using the wrong mask, incorrectly setting the implant dose—as well as from physical sources: contaminated chemicals, dirty etch sinks, or a troublesome process step. It is possible to repeat or rework some of the reversible steps (a lithography step, for example—but not etching) if there are problems. However, reliance on rework indicates a poorly controlled process. 14.3.1 Reliability It is possible for defects to be nonfatal but to cause failures early in the life of a product. We call this infant mortality . Most products follow the same kinds of trend for failures as a function of life. Failure rates decrease rapidly to a low value that remains steady until the end of life when failure rates increase again; this is called a bathtub curve . The end of a product lifetime is determined by various wearout mechanisms (usually these are controlled by an exponential energy process). Some of the most important wearout mechanisms in ASICs are hot-electron wearout, electromigration, and the failure of antifuses in FPGAs. We can catch some of the products that are susceptible to early failure using burn-in . Many failure mechanisms have a failure rate proportional to exp (– E a /kT). This is the Arrhenius equation , where E a is a known activation energy (k is Boltzmann’s constant, 8.62 ¥ 10 –5 eVK -1 , and T the absolute temperature). Operating an ASIC at an elevated temperature accelerates this type of failure mechanism. Depending on the physics of the failure mechanism, additional stresses, such as elevated current or voltage, may also accelerate failures. The longer and harsher the burn-in conditions, the more likely we are to find problems, but the more costly the process and the more costly the parts.
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  • Fall '15
  • prasad
  • Logic gate, NOR gate, fault simulation

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