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Note 2_ A review on Verilog basics.pdf - SYSC 4310:...

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SYSC 4310: Computer SystemsArchitectureLecture 2: A review onVerilog basicsRose GomarDepartment of Systems and Computer Engineering
Today:Basics of Verilog HDLImportant constructsTestbench design
VerilogHardware Description Language (HDL)Chips are designed using HDLsFPGAs or ASICsField Programmable Gate ArraysApplication Specific Integrated Circuit
VerilogLanguage offers 2 types of constructs:SynthesizableUsed for design and implementation (synthesis)Used for simulationNon-synthesizableUsed for simulation
VerilogIn every lab:TestbenchAll language constructsDevice Under TestSynthesizable constructsGenerate inputsMonitor outputs
VerilogDifferent levels of designGate levelData flowStructural designRegister-Transfer level (Behavioral model)SyntaxA set of rules, if broken you get errorsStyleMany different coding stylesDifferent levels of abstraction
VerilogDesignfor synthesis: Device Under Test (DUT)Simulationfor testing: Testbenches
Verilog Design: Top level
Verilog Design: Top levelModule declarationInput/output list
Verilog Design: Top levelModule declarationInput/output listInput/outputDirection, size
Verilog Verilog Design: Top levelModule declarationInput/output listInput/outputDirection, sizeBodyFunctionality
Verilog Design: Module BodyCombinationalWire declarationsAssignmentsSequentialRegister declarationsAlways blocksHierarchySub-module instantiation

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Term
Fall
Professor
N/A
Tags
Input output, Application specific integrated circuit

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