let4-Adders

Computer Arithmetic: Algorithms and Hardware Designs

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CSE 246: Computer Arithmetic Algorithms and Hardware Design Instructor: Prof. Chung-Kuan Cheng Lecture 4: Adders
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CSE 246 2 Topics: Adders AND/OR gate v.s. Circuit Logic Design Graph Design (Prefix Adder)
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CSE 246 3 Chapter 2: ADDERS Half Adders Half adders can add two 1-bit binary numbers when there is no carry in. If the inputs are x i and y i , the sum and carry-out is given by the formula s i = x i ^ y i c i+1 = x i . y i We use the following notations throughout the slides . means logical AND + means logical OR ^ means logical XOR ‘ means complementation
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CSE 246 4 Full Adder The inputs are x[i], y[i] (operand bits) and c[i] (carry in) The outputs are s[i] (result bit) and c[i+1] (carry out) Inputs and outputs are related by these relations s[i] = x[i] ^ y[i] ^ c[i] c[i+1] = x[i].y[i] + c[i].(x[i] + y[i]) = x[i].y[i] + c[i].(x[i] ^ y[i])
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CSE 246 5 Full Adder If carry-in bit is zero, then full adder becomes half adder If carry-in bit is one, then s[i] = (x[i] ^ y[i])’ c[i+1] = x[i] + y[i] To add two n-bit numbers, we can chain n full adders to build a ripple carry adder
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CSE 246 6 Ripple Carry Adder x[0] y[0] cin/c[0] s[0] . . . x[1] y[1] c[1] x[n-1] y[n-1] c[n-1] s[1] c[2] s[n-1] cout Overflow happen when operands are of same sign, and the result is of different sign. If we use 2’s complement to represent negative numbers, overflow occurs when (cout ^ c[n-1]) is 1
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CSE 246 7 Ripple Carry Adder For sake of brevity, we use the following notations: g[i] = x[i].y[i] p[i] = x[i] + y[i] In terms of these notations, we can rewrite carry equations as c[1] = g[0] + p[0].c[0] c[2] = g[1] + p[1].c[1] and so on… We shall use these notations afterwards while discussing the design of other kind of adders It has been observed that expected length of carry chain is 2, while expected maximal length of carry chain is lg n. Hence, ripple carry adders are in general fast.
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CSE 246 8 Ripple Carry Adder How do know that an adder has completed the operation? Worst case scenario: Wait for the longest chain in the carry propagation network We might inspect c[i+1] and its complement b[i+1] to determine the status of the adder Don’t care 1 1 Complete 1 0 Complete 0 1 Not complete 0 0 Remark b[i+1] c[i+1]
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CSE 246 9 Improvement to Ripple Carry Adder: Manchester Adders By intelligently using our device properties, we can reduce the complexity of the circuit used to compute carries in a ripple carry adder. Define: a[i] = (x[i])’.(y[i])’ Next we observe that c[i+1] is 1 in exactly these scenarios: g[i] is 1, i.e. both x[i] & y[i] are 1 c[i] is 1 and it is propagated because p[i] is 1 c[i+1] is ‘pulled down’ to logic 0 irrespective of the value of c[i], when a[i] is 1, i.e. both x[i] and y[i] are 0 From these conditions, and keeping in mind the general characteristics of transistor devices we can design simplified circuits for computing carries – as shown in the next slide
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CSE 246 10 Improvement to Ripple Carry Adder: Manchester Adders VDD g[i] p[i] c[i] a[i] c[i+1]
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CSE 246 11 Implementation of Manchester
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let4-Adders - CSE 246: Computer Arithmetic Algorithms and...

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