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# hw4 - Daniel Lau EE271 SID 005299776 Hw#4 module...

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Daniel Lau EE271 SID: 005299776 Hw#4 module function1 (A, B, C, D, Out1, Out2); input A, B, C, D; output Out1, Out2; wire f1a_temp, f2a_temp, f3a_temp, f4a_temp, f5a_temp, f6a_temp; assign Out1 = f1a_temp | f2a_temp | f3a_temp; assign Out2 = f4a_temp | f5a_temp | f6a_temp; and f1a (f1a_temp, ~A, B); and f2a (f2a_temp, A, ~B, C, D); and f3a (f3a_temp, B, ~C); and f4a(f4a_temp, ~A, ~B, C, ~D); and f5a(f5a_temp, ~A, ~C, D); and f6a(f6a_temp, ~A, B, C); endmodule `timescale 1ns/100ps //Out1 = min(4,5,6,7,11,12,13) //Out2 = min(1,2,4,5) module testbench; reg A, B, C, D; wire Out1, Out2; integer i; function1 my_function1(.Out1(Out1), .Out2(Out2), .A(A), .B(B), .C(C), .D(D)); initial begin #10

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for (i = 0; i <= 4'hf; i = i+1) #10 begin {A, B, C, D} = {i}; end #20 \$finish; end endmodule 2. module Add_full (sum, c_out, a, b, c_in); output sum, c_out; input a, b, c_in; wire w1, w2, w3; xor sum_g(sum, a, b, c_in); and cout_g(c_out, w1, w2, w3); and w1_and(w1, a, b); and w2_and (w2, b, c_in); and w3_and (w3, a, c_in); endmodule
`timescale 1ns/100ps module testbench; reg a, b, c_in; wire sum, c_out; integer i; Add_full my_add(.sum(sum), .c_out(c_out), .a(a), .b(b), .c_in(c_in)); initial begin #10 for (i = 0; i <= 4'h8; i = i+1) #10 begin {a, b, c_in} = {i}; end #20 \$finish; end endmodule

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