hw3 - Daniel Lau EE271 HW3 1a `timescale 1ns/100ps module...

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Daniel Lau EE271 HW3 1a `timescale 1ns/100ps module yverilog (A, B, C, D, Y); input A, B, C, D; output Y; wire temp1, temp2, temp3; or M1 (temp1, A, D); //(A+D) not M2 (temp2, temp1); //~(A+D) not M3 (temp3, temp2); //~D and M4 (Y, temp3, temp2, B, C); //assign Y = (~(A + D)) & (~D & B & C); endmodule 1b. primitive yverilog_prim (Y, A, B, C, D); output Y; input A, B, C, D; table //A B C D : Y 0 0 0 0 : 0;
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0 0 0 1 : 0; 0 0 1 0 : 0; 0 0 1 1 : 0; 0 1 0 0 : 0; 0 1 0 1 : 0; 0 1 1 0 : 1; 0 1 1 1 : 0; 1 0 0 0 : 0; 1 0 0 1 : 0; 1 0 1 0 : 0; 1 0 1 1 : 0; 1 1 0 0 : 0; 1 1 0 1 : 0; 1 1 1 0 : 0; 1 1 1 1 : 0; endtable endprimitive `timescale 1ns/100ps module testbench; reg A, B, C, D; wire Y; wire clk; //for control signals yverilog_prim my_yverilog ( .Y(Y), .A(A), .B(B), .C(C), .D(D) ); initial begin #10 {A, B, C, D} = {1'b0, 1'b0, 1'b0, 1'b0}; #10 {A, B, C, D} = {1'b0, 1'b0, 1'b0, 1'b1}; #10 {A, B, C, D} = {1'b0, 1'b0, 1'b1, 1'b0}; #10 {A, B, C, D} = {1'b0, 1'b0, 1'b1, 1'b1};
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#10 {A, B, C, D} = {1'b0, 1'b1, 1'b0, 1'b0};
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This note was uploaded on 05/06/2008 for the course EE 271 taught by Professor Thuyle during the Spring '08 term at San Jose State University .

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hw3 - Daniel Lau EE271 HW3 1a `timescale 1ns/100ps module...

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