design_notes

design_notes - Memory wr_en = 1 mem_addr_sel = 0(dest_data...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Sheet1 Page 1 Err:510 pc_wr = 0 wrbck_sel = 1 src_sel = 1 CPR: ALUout = op1 since op1 is src register ALUout is fed back to wr_bckdata, we = 1 alu_out back to wr_bckdata, we = 1 NOT: alu_out = bitwise complement of op1 ALUout is fed back to wr_bckdata, we = 1 Err:510 RDM: src_sel = 0 (select addr to be address register) dest_sel = 1 wrbck_sel = 0 Memory rd_en = 1 mem data_sel = x mem_addr_sel = 0 we = 1 WRM: src_sel = 0 dest_sel = 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Memory wr_en = 1 mem_addr_sel = 0 (dest_data) mem_data_sel = 1 (src_data) ADD/SUB: alu_out = op1 + op0 / alu_out = op0 - op1 alu_out back to wr_bckdata, we = 1 dest_sel = 1, src_sel = 1 JMP: src_sel = x dest_sel = 0 pc_wr = 1 pc_data_sel = 0 JMZ: src_sel = 2dest_sel = 0 pc_wr = zeroflag pc_data_sel = 0 LPC:dest_sel = xsrc_sel = 1 pc_wr = 1pc_data_sel LDR:src_sel dest_sel = 1 ldr_sel Sheet1 Page 2 dest_sel = 1...
View Full Document

{[ snackBarMessage ]}

Page1 / 2

design_notes - Memory wr_en = 1 mem_addr_sel = 0(dest_data...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online