# PS_Chapter4 - Chapter 4 Problems 13.04.2016 For More...

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Chapter 4 Problems 13.04.2016

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For More Practice
Single Cycle Datapath

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Exercise 5.21 Put a new mux right before branch AND gate. There will be a new selector signal for this mux (call it as InvZero ). Connect zero and inverted zero inputs to the new mux.
Single Cycle Datapath

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For More Practice R-format load word lw rd, rs, rt RegDst ALUsrc MemtoReg RegWrite MemRead MemWrite ALUop 1 0 1 1 1 0 10
4th Edition

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Single Cycle Datapath
Exercise 4.8.1 a. 7th bit immediate, offset Addi \$1, \$zero, 128 \$1 128 0000...00001000000 If \$1 = 0, there is stuck-at-zero fault ! b. MemtoReg register write data input comes from data memory (load) lw \$1, 1024(\$zero) # Assume that data memory full of zeros If \$1 = 1024, there is stuck-at-zero fault ! 7th bit

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4th Edition
Single Cycle Datapath

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Exercise 4.10.1.a Critical Path path to get the data for a load instruction. Load I mem + Mux + Regs + Mux + ALU + Dmem + Mux 1 CC = 400 + 30 + 200 + 30 + 120 + 350 + 30 1 CC = 1160 ps. I mem 400 ps 1160 400 = 760 ps. MemWrite signal should be generated in 760 ps w/o lengthening the critical path of the datapath. Exercise 4.10.2.a MemWrite and RegWrite. Both of them are at the end of clock cycle !
4th Edition

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Single Cycle Datapath
Exercise 4.10.3.a I. RegWrite , MemWrite end of the cycle II. RegDst, Jump, MemtoReg 1 mux latency before end III. Branch 2 mux latency before end IV. MemRead 1 Dmem + 1 mux latency before end V. ALUop ALUCtrl + ALU + Dmem + mux latency before end VI. ALUsrc 1 mux + ALU + Dmem + mux latency before end According to their criticality; a. ALUCtrl latency > Mux latency ALUop is the most critical.

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