SequentialCircuitsLecture

# SequentialCircuitsLecture - Sequential Circuits • Models...

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Unformatted text preview: Sequential Circuits • Models for representing sequential circuits – Finite-state machines (Moore and Mealy) – Representation of memory (states) – Changes in state (transitions) • Design procedure – – – – – State diagrams Implementation choice: counters, shift registers, etc State transition table State encoding Combinational logic » Next state functions » Output functions Abstraction of State Elements • Divide circuit into combinational logic and state • Localize feedback loops and make it easy to break cycles • Implementation of storage elements leads to various forms of sequential logic Forms of Sequential Logic • Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) • Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Mealy and Moor.. • Mealy: output depends on input and state • Moor: output depends only on state FSM Representations • States: determined by possible values in sequential storage elements • Transitions: change of state • Clock: controls when state can change by controlling storage elements • Sequential Logic – Sequences through a series of states – Based on sequence of values on input signals – Clock period defines elements of sequence Example: Sequence Detector • Desired – A circuit that outputs when a specific sequence is detected – Assume (for rest of the semester) sequential circuit for timevarying computation unless otherwise specified – Pattern to detect: 0101 – input: .01010100010101010 – Overlap or not? Can Any Sequential System be Represented with a State Diagram? • Shift Register – Input value shown on transition arcs – Output values shown within state node Counter Example • Shift Register – Input determines next state Counters are Simple Finite State Machines • Counters – Proceed thru well-defined state sequence in response to enable • Many types of counters: binary, BCD, Gray-code – 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... – 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ... module binary_upcntr (q, clk) inputs clk; outputs [2:0] q; reg [2:0] q, p; always @(q) case (q) 3’b000: 3’b001: … 3’b111: endcase // Next state p = 3’b001; p = 3’b010; p = 3’b000; always @(posedge clk) // Update state q <= p; endmodule More Complex Counter Example • Complex Counter – Repeats five states in sequence – Not a binary number representation • Step 1: Derive the state transition diagram – Count sequence: 000, 010, 011, 101, 110 • Step 2: Derive the state transition table from the state transition diagram " &' ( ' & )* & ! \$ "\$ #\$ # ' % % % % % % % % % ' More Complex Counter Example (cont’d) • Step 3: K-maps for Next State Functions \$ "\$ #\$ + # + + + # + + " " \$ # "\$ "(\$ #(( #\$ " ( + # + + " Self-Starting Counters (cont’d) • Re-deriving state transition table from don't care assignment \$ "\$ #\$ # # # " " " # ! \$ "\$ #\$ " Self-Starting Counters • Start-up States – At power-up, counter may be in an unused or invalid state – Designer must guarantee it (eventually) enters a valid state • Self-starting Solution – Design counter so that invalid states eventually transition to a valid state – May limit exploitation of don't cares * ,* - , ' State Minimization • Fewer states may mean fewer state variables • High-level synthesis may generate many redundant states • Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same • Two conditions for two states to be equivalent: – 1) Output must be the same in both states – 2) Must transition to equivalent states for all input combinations Sequential Logic Summary • Models for representing sequential circuits – – – – Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines • Finite state machine design procedure – – – – Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic ...
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