Exercises 4 - 4.16 Exercises of some of the inventions...

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4.16 Exercises of some of the inventions since the mid -1990s, resulting in a simplification of pipelines in the more recent versions of microarchitectures. To sustain the advances in processing performance via parallel processors, Amdahl's law suggests that another part of the system will become the bottleneck. That bottleneck is the topic of the next chapter: the memory system. 409 Historical Perspective and Further Reading This section, which appears on the CD, discusses the history of the first pipelined processors, the earliest superscalars, and the development of out -of-order and speculative techniques, as well as important developments in the accompanying compiler technology. Exercises Contributed by Milos Prvulovic of Georgia Tech Exercise 4.1 Different instructions utilize different hardware blocks in the basic single-cycle implementation. The next three problems in this exercise refer to the following instruction: Instruction Interpretation a. add Rd,Rs,Rt Reg[Rd]=Reg[Rs]+Reg[Rt] b. lw Rt,OffsCRs) Reg[Rt]=Mem[Reg[Rs]+Offs] 4.1.1 [5] <4.1> What are the values of control signals generated by the control in Figure 4.2 for this instruction? 4.1.2 [5] <4.1> Which resources (blocks) perform a useful function for this instruction? 4.1.3 [10] <4.1> Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?
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410 Chapter 4 The Processor Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks. Latencies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruction. For the remaining three problems in this exercise, assume the following resource latencies: .. _-_ .. _- 4.1.4 [5] <4.1> What is the critical path for a MIPS AND instruction? 4.1.5 [5] <4.1> What is the critical path for a MIPS load (LD) instruction? 4.1.6 [10] <4.1> What is the critical path for a MIPS BEQ instruction? Exercise 4.2 The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing ISA, but the decision whether or not to do that depends, among other things, on the cost and complexity such an addition introduces into the processor datapath and control. The first three problems in this exercise refer to this new instruction: Instruction Interpretation a. add3 Rd,Rs,Rt,Rx Reg[RdJ=Reg[RsJ+Reg[RtJ+Reg[RxJ b. sl1 Rt,Rd,Shift Reg[RdJ= Reg[RtJ « Shi ft (shift left by Shift bits) 4.2.1 [10] <4.1> Which existing blocks (if any) can be used for this instruction? 4.2.2 [10] <4.1> Which new functional blocks (if any) do we need for this instruction? 4.2.3 [10] <4.1> What new signals do we need (if any) from the control unit to support this instruction?
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