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**Unformatted text preview: **3. Energy—Delay Optimization Consider a symmetrically-sized inverter driving another, identical inverter trough a wire with
a ﬁxed capacitance C117 = 12fF, as shown in Figure 3. In this technology, VDD = 1V, Cg:
Car = 2fFr’u1n, transistor thresholds are 0.25V and fanout-of—4 invelter delay is 20ps. inv, ””2 CG CG
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I C" T Figure 3. a} How would you size the inverters to minimize the energy? b) How would you size the inverters to minimize the delay? c) How would you minimize the inverters to minimize the energy-delay product of the ﬁrst
inverter, fin-’1 ‘9 d) If the input capacitance of the ﬁrst inverter is set to CI = 6fF, the wire capacitance Cw is
12fF, how would you size the second inverter that is driving 27fF load to minimize the overall delay from In to Out in Figure 4? Explain the result. Inv, “”2
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Wm: LN.ONL"\ “W l voi-LS. Problem 3 (5 points) For the inverter buffer chain below, assume the optimal fanout factor is f= 4.4 and a minimum size inverter has Wn = 045th and W1) = 1.35 pm. How
many stages N are required for a minimum delay through the chain and what are the
transistor widths for the final inverter in the chain? N: IS 01” G I
wn (th inverter) =— wp(Nthmvener)=t_3’::]o Mo; 1mm F: 9:: 3w J {'29 c3.
----- to: NW) :twlam‘l
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(6— 13 WP ; [L3f3/Am3 [L4H Problem 1.1 Moore’s Law for hﬁcroproceseors. Figure 1 shows a plot of transistor
count for mieroproeessors through EDGE [£1]. Based on the etrvztthio113.11,.r trends described in Chapter 1 of Hahstey1 predict the integration lectuzlpleotit}.r and the clock speed of a micropro—
cessor in the years 24311], 21315, 24121], and 21:95. How does. your ‘Eﬂlﬂ prediction compare to
the data in the Moore‘s Law graph From lecture [which runs through 3311}? CPU Transistor Counts 1971-2003 8: Moore’s Law 2.000.0uomo— mm“... :W““‘
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1971 19:0 19m 2000 anus Data at introduction 1.1 Here, we can derive a formula for exponential gromh.
x1 =xu +xumr; (1}
where x0 is the starting amount, r is the rate of growth or decay, and x1 is the new amount
if the growth or decay is repeated at a regular interval, we can write the expressions below for the second growth or decay, x2 = x1 + x1 * r; {2) for the nth growth or decay, x“ = xn_1 + xn_1 Ir r;
Substituting [1) into (2) and we obtain the following, x2 = x0 + 2x0r + :i:.;;r2 = xu(1 + r)2
Generalizing this expression. we obtain 3! = x(1 + r)"
where x is the starting value,n is the number of times 1 grows.
r is the rate of growth, and y is the final value.
Note: this is the same formula for calculating compound interest.
Integration complexity assumes growth o f 4x (r = 3) every 3 years as on page If of Rahaey. Starting with 400M transistors in year 2005. 5
@2010 —> n = 5,}! = 400 it 105(4)§ E 4 billion transistors
@2015 —> n = 10, y = 400 * 105(4jl'3r'3 e 40 billion transistors
@2020 —> n = 15,}! = 400 x 10599133 E 400 billion transistors @2025 —> n 2 20,3: 2 400 it 105(4):”?! E 4000 billion transistors Irmag'mion Dnrnplaxi‘ly ill: arm
or. imam-I #22015 ;
Tina-1940105 hhrnharof Tmnsiatnrs ‘r'ear Frequency assumes growth of 2.1: [r = 1]: every 2 years. Starting with IGHz in 2611111 in
@2010 —r n = 10.3: = 1 1: 109(2)? E 3.2 a 1131“ Hz
@2015 —> n = 15,y E 131G * 1911 Hz
@2020 —> n = 20,}? E 11324- * 1013 H2.“ @3125 —r n = 25.3: E 5.? t ll'll12 He M Black Frequency 10 1D” 1cm
1r":1l:l3i:1-lll"l3 _-.
III
E 323315 "r": 1 B1 B+l]1‘l Frequency EIIIEI EIIE 21310 11115 1113!] SEE III-Ill
‘r'ear From lecture I slide #15, theaverage ounrheroftransistors on a single die in year 21119 is approx. ll] billion. Dn slirh #lﬂ it is approx. 2 to 2.6 billion Our periclion is appros. 4 billion transistors in Mill
which is in the same rang. as tJE. data. Moore’s law for integration oon‘qﬂesity is fairly accurate. Do the od'ier hand, clock frequencies have saturated at aroturd 3 to 5 GI-le, no longer following Moore’s
law. A corlinuod increase in clock rate will cause digital systems to dissipate Lulaoceptable amour! of
power. Additionally, the overhead and cost to reliably deliver clock signals is too high at extremely high frequencies To corrpensate for the saturaling clock frequency, microprooessor’s throughput is usually
n'nintaired by adding additional processing cores. [5] Leakage 10 marks
Find the subtlneshold clurent for a NAND gate built from unit transistors, i.e. {WKLJP = 4. (WILL = 2.
Assume inputs A=E=tl Show ttrat the sulrthreslrold crurent through the series transistors is half that of an
inverter if n. = 1. 5) If all transistor sizes are the same, and if all inputs are low (Le. 11]), which of the following
logic gates has the highest static energy dissipation? ....................................... |:|
{a} Inverts
{bi HAND
{c} NOR.
{d} Tristate inverter [11. Logical Effort 5 marks
Forthe conventional CMDS logic gate implementing Z = (A + BCHE + F) ﬁnd 3:: and g fordiflinent
inputs Figure ‘2: Cascade-cl inwrter and NAND gate forming part of a logic network. Pruhiem 2.5 [1 point] Figure 2 skews a (III-IDS inverter tithing a EMF wire lead and a.
2—input NAND gate driving a mﬂﬂ“ wire load. You will use the method of Inglcal effort to
minimiee the delay of these gates by ﬁnding the eptime‘t transistor widths. First. ﬁnd the
normalized parasitic delay :3 = 6,me from the values you found above. _ CE _ Iain: = '3
'3”— c:.«. ‘ H.‘iUF'F 1' 5
Problem iii {5 points] Find the optima} transistor uddthe fer the FETe in Figure ‘2 assuming each logic stage has an identical effort delay 1’ = gh of =1. ' WPA=515
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{.n: ELS'H'_._ EGMFF; Stale at l' ”Inﬁni} HEN“: L True-False Questions ll] 3-: l = It] marks Print True ('1) or False (F). whicirrver is more appropriate, in the box following each statement. 1) Dining the discharge of an outprrt node (in a logic gab) the errerjgyr stored in its capacitance is dumped into ground . ................................................................ |:|
2) Logical effort 9 is independent of the size of the transistors in a logic gate. .................. |:|
3) Gate leakage of PMCIS transistors is lower than NMDS transistors of the same tam. ........... |:|
4) The larger the transistors in the critical patir of a circuit, the lower the delay. ................. |:| 5) The dynamic power dissipation of a HAND gat: whose one input is grounded, equals zero. . . . |:|
6) Method ofLogical Effort is used to optimize ﬂirt: power dissipation in a digital craos circuit. . |:| T) High Vi transistors can he used in non-critical paths to save energy. ......................... El 3) Instantaneous power is used to determine the wire thickness . .............................. |:| 9) A digital circuit sized for minimum delay, has the maximum power consrunption. ............ |:|
1D) The ratio of the stored energy at the output capacitance of an inverter to the heat dissipated by its esros transistor is r. ............................................................. |:| IL Multiple Choice Questions Print the letter corresponding to the most appropriate answer in the box. 1) If the optimum nurnher of inverters driving a load is 5. and the input capacitance of the ﬁrst invemr
is 3 unitsI what is the input capacitance of the last inverter? ................................ |:| (a) 1.5
(tr) T63
(C) 43
(d) 1315
2) If we ignore the parasitic delay of inverters, the optirnrun stage effort is ...................... |:|
(a) 4.
{b} 5r-
(c) e.
(d) 2.
3) Short-circuit power dissipation is typically about of the total dynamic prover? ............ |:|
(a) 10%
{b} 30%
(c) 50%
(d) ”Hits: 4) Decreasing which pararnetir among the following is most effective in reducing dynarrric
power dissipation?r ..................................................................... |:|
ta) Frequency
(h) Switching activity
{c) Prayer supply voltage
{d) Effective capacitance [4] [15 matte) Impiemem the following ﬁmclion in cammticnal mes. Assume that both the tmc and
inverted inputs are available IftheIe are more than one possible implementations, duo the clue that imposes
lees capacitive 1035 at the mﬂput, be, faster. - Z=A[B+(I]+FJE - Sizethetansistmemchthatﬂaelogjc gateisequi‘caleﬂt [inresistanee andcmrentﬁuaunitimrerter
{Le H’FELP = '2 and HEW-“Ln = 1). [fthcieare mere than enemy ofsizzing, :10 the methat results
inafaeter circuit. I [fﬂaenmpmdiﬂiisioncapacitanceufauuitimreiteris 12E, calclﬂatetheenergjrdissipaﬁmatttm I Hmtrccmchpawerdumsavebyupemﬁngwithapmmppljreflﬁvinstead efLEtr. 5. List 3 reaeons why the design of interconnect has become more import-mat
more critical over the past few yen-Ms.2 3 marks ———_________
1 I I
Gradmg policy: you get 5 marks for not answering this question, 0 ks r ' ' ,
5 marks fr” 3' mm“ Ema, 4 marks for 2 lightfl wm’rlg. etc. my M gwmg 3 mm“ "m“ 4. A 1x unit-sized inverter drive; a. 20x inverter at. the end of a. 2.5 mm
wire. ' A unit inverter in this process has an effective resistance of 6.9 #51 on both the pull up device and the pull down deﬁce; the unit inverter has
a gate capacitance of 2 ft". The wire is 0.32pm wide; its Sheet rte-stance is 0.05 ﬂfEI, and capaci—
tance to ground is 0.2 Ing'pm. II Compute the propagation delay,r for the above system. . If you could change the width of the wire, whet width would you
use to minimize the propagation delay? 20 marks (3][Elmoreﬂe1a3,5pnints] ComputeElmnredelajratSink l and Sink? inthe
following ﬁgure.
cam ottn em: I 4” $40“: $10“: W} = Vm'ulll 2m Driltﬂ 0.1M! [Hm Sink'l 15F IEEI'F leer :1;er law I25”:
Sink 1; T = nit : [25)“ + 5}”) + nit : {25f + 25;“ + 5f} + 0.11: * [25)" + 25;" +
25f+ 5f) +0.1k * (25f+ 25f +25f+ 25f+ 5f+tcf+4of+ inf) + nit: *
(the whole dwmtrenm cap = 2201”) + 2k * ZZDf = 3:15 + 5.5p5 + Bps + 19.5p3 + 22;): + 44ﬂp3 = 493m Sink 2: t = 0.5;: * (40f + 1ch+ 0.5;: * (tar + 40;" + 1oﬂ+ Illk * {25f + 25f +
25f + 25f + 5f+4ﬂf + tcf+ 10f] +0.11: : 220;" + 2;: a: 220;" = 25103 +453“ +
19.51.15 + 22;): + 44ﬂps 2 551.5133 ...

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