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Unformatted text preview: Example 1.2
Sketchastaﬁc CMDS gatecompuﬁl'rgY=I:diB+C}*D. SDliﬂlllH: Figure 1.19 shows such an DR—AND—WVERT—E—l {0.3131} gate. The
nMCIS Pall—dmennetwrlrpullsﬂleontputlmeifﬂh landeitllerzforBor Care 1,I
soDisinseﬁeswiﬂlﬂJeparaﬂeloomhhtaﬁonofA,B,aodC.ThepMUS pull—up net—
work is the conduch'mt complement. so D must he in Parallel wiﬂl the series combina—
FIGURE 1.19 MOP—4'3 aﬂd ‘1 llﬂ An nli‘IDS transistor has a ﬂiresholrl voltage of'DA V and a suppl].r voltage oFFDD=
LEVER circuit designeris evaluaﬁng a proposal to rednoe ﬂhf IEIJ'mV to obtain
Faster transistors. a] By what Factorwoulrl the saturation current increase [at FEE: ﬂ = FED} ifthe
transistor 1.Iirere ideal? h] By what faetor would the suhﬂlreshold leakage current increase at room tempera—
ture at 321:"? Asstnne n: 1.4. :1! By what factor would the suhﬂrreshold leakage current increase at 120 "C?
Assume die threshold voltage is independent ofternperanrre. 2.1: (a) [1.2 — he]:2 I (1.2 — 114]:2 = 1.25 [25%) —i.l'.3
f: 1.4 I [11326
1.4 I [1026‘
E
413
€1.4 . ﬂ.ﬂ34
(c) VT = kilo = 34 mV; T = 3.2 ; note, however, that the total leakage
1.4 ! 0.1334
6 will normally.I be higher for both threshold 1voltages at high temperature. 5 .3 The stack eﬁ'ect causes the current through two series OFF transistors to be an order of magnitude less than Ioﬂrwhen DIBL is signiﬁcant. Show that the current is Iﬂﬂn’l
when DIBL is insigniﬁcant (e.g., T] = D}. Assume T: U, n = 1. 5.3 Simplify using VDD >> VT: 3.1 3.1 A 243 um UV step and scan machine costs $10M and can produce 30 3111} mm
diameter, 91} nm node wafers per hour. A 193 nm UV step and scan machine costs 340M and can process 20 300 mm diameter, 50 nm node wafers per hour. Ifﬂie
machines have a depreciation period of four years, what is the diﬁ'erence in the cost per chip for a chip that occupies 50 square mm at 90 nm resolution iftbe stepper is
used 10 times per process run for the critical layers? First, the cost per wafer for each step and scan. 243nm — number ofwafers for four
years = 4*355‘24‘30 = 2,303,200. 193111.11 = 4*355‘24‘20 = T00,300. The mat per
wafer is the (equipment cost]f(number of wafers] which is for 243nm $10M:f
2,303,200 = 33.515 and for 193nm is $40Mnﬂ0,300 = $53.03. For a run through the
equipment 10 times per completed wafer is $35.50 and $520.71? respectively. Now for gross die wafer. For a 300mm diameter wafer the area is roughly
sass:1 m2 {n*[ M — ﬁ(sqrt(2"A))). For a shaman2 die in 90mm, there are 13:55
gross die per wafer. Now for the tricky part (which 1was unspeciﬁed in the question
and oould cause oonfusion]. What is the area of the 50nm chip? The area of the core
will shrink by (‘5101'5032 = .3036. The best case is if the 1Whole die shrinks by this fac—
tor. The shrunk die size is 50*.3036 = 15.43mm2. This yields 4495 gross die per
wafer. The cost per chip is $35.60;“ 1413 = 30.020 and 3520.331'45713 = $0.127Ir respectively
for 90nm and 50pm. So roughly speaking, it costs $0.10 per chip more at the 50nm node. Obviously, there can he variations here. Another way of estimating the reduoed die
size is to estimate the pad area {if it's not speciﬁed as in this exercise) and take that
out orthe equation for the shrunk die size. A 50mm2 chip is roughly Tmm on aside
(assuming a square die). The HG pad ring can be (approximately) between 0.5 and 1
mmper side. So the core area might range from 25mm2 to 30mm? When shmnlc,
this core area might vary from T? to 11.1mm2 (2.2? and 3.33mm on a side respec
tively). Adding the pads back in (they don't scale very much], we get die sizes of
4.2? and 4.33 mm on a side. This yield possible areas of 13.? to 22.3 mg, which in
turn yields a cost ofprocessing on the stepper ofbetween 30.155 and $0.139. This is
a rather more pessimistic (but realistic) value. 5.111] For a 2% delay increase, the supply should droop by less than about 2% of VDD (cg. 2t] mV @ Lt} V). Thus the eHecnve resistance must he R. = 2t] me 10!} midi. =
0.2 Q. Thisrcquires awidthofw=15 kt?!" umi'tlﬂ G: 12.5 mm. 5.10 Design a header switch for a power gating circuit in a 65 can process. Suppose the pMOS transistor has an ON resistance of about 2.5 M). ' pm.The block being gated
has an ON current of 100 mA. How wide must the header transistor be to cause less than a 2% increase in delay? 6.4 Find the best width and spacing to minirnice the RC delay of a metalZ bus in the
130 nrn process described in Figure 6.12 if the pitch cannot exceed 960 nm. Mini
mum width and spacing are 32H nrn First, assume that neither adjacent bit is
switching. How does your answer change if the adjacent bits may be switching? 5.4 a = coarser; c: F0017, 5);W+s=1oou nm. are: 5) is found from Table 4.3. The‘3' adj term is doubled if the adjacent hits might switch in the opposite direciton. [fneighhors are not switching, choose 5' = 320 um and W: 630 um. [fneighhors are
snatching, choose 3: Slit] nm and W: Slit] nm. In the ﬁrst case, resistance domi
nates so the wide wire is fastest. In the second case, the coupling capacitance is exacerbated by the switching neighbors, so increasing the spacing is most useful. Example 4.13 Estimate themininmmdelaynfthe path fromAtoBin Figure4.31
and choosetransistor sizestoachieve this delayThehdﬁalNANDZ
gate may present a load ofB l. oftransistor 1I.II'idt:: on the input and
the output load is equivalent to 45 l. nftransistorwidth. SOLUTION: The path logical eﬁ'ort is G: [#3] x [SIS] x [SIS] = 1W
2?.The path electrical eifort is H: 454I’B.The path branching eﬁbrt
isB=3x 2:5.The path effortisf: GBH: 125.1% thereare
threestages,the heststageeﬁ'ortis f: 125:5.Thepathpara—
siticdelayisP=2+3+2=?. Hence,theminirnumpathdelayis
D = 3): 5 + 'i' = 22 in units of't', or 4.4 F04 inverter delays.The
gate sizes are computed with the capacitance transformation from
EQ{4.41] worldng backward along the path: y = 45 x {SISM = 15.
a: = {15 + 15) 3: {SHEHS = II]. We verify that the initial 2—input
NAND gate has the speciﬁed size ofﬂﬂ+ ll] + IUD(($315 = B.
The transistor sizes in Figure 4.32 are chosen to give the desired
amount nfinput capacitance 1while achieving equal rise and fall
delays. For example. a 2—input NOR gate should have a 4:1 PIN
ratio. Ifthe total input capacitance is 15, the pMOS width must be
12. and the rIMUS width must be 3 to achievethat ratio. Wecan alsocheckdtatmuddaywasachkvedTheNﬂNDZ gate
delayis d1=glﬁl+p1=ﬂtﬂlx [10+1u+1u)!s+2=r.m HANDS FIGURE 4.32 Exampta path annonrtad with
transistor sires gatedeiayisdl=m+m =[5J'3])<{15+ 1W1I1+ 3: 81.1111: NOR2 gatedeiayis d1: 33b3+p3=ﬁﬂﬁx4915+2=T.Hence,dlepadldeiayis22,aspredicmd.
Recailﬂiatdelayis erpressedirlurlitxof'r. In aIESurnprocesswith1:31:s,thied1ela].I isﬁéps.Altermﬁvelﬁaﬁnuut—of~4imerterdelajris 5!,sothepad1deiayis4d F045. Example 4.14 Acontroi urlitgenerates asignal ﬁorn aunit—sized invertec'I’he signal rnustdtive
unit—sized loads in read: hitsiiee ofa lISA—hitdatapatl:.'1"l'1e designer can add invert—
ers to huEer the signal to drive the large load. Amming polarity of the signal
does not mattenwhat is the hestnurrlher ofirnrerters to addarldwhat delaycarl
be adlieved? SDLUTIIJN: Figure 4.33 shows the cases of adding I], l, 2, or 3 imlertemThe pad]
electrical eﬂhrt is H: 64. The path logical eﬂiort is G = 1, independent ofthe
nurnberofinverters.Thus,ﬂJepath effortisF=64.'Iheinvertersizes areehoserl
toadiieve equal stage eﬁhrLThe total delayis D=Nﬁﬁ+m TheB—stage designisﬁlstest andfarsuperiortu a single stageJIan even nurn—
herofinrlersionswererequired,d1e two— orfour—stage designs arepromisirlg.The
Four—stage design is slightlyY faster, but the tum—stage design requires signiﬁcanﬂy FIGURE 433 Comparison Of different
less area and . number afstages of More 6.7 lCompute the characteristic velocity (delay per mm} of a repeated metall wire in the
133' nm process. A unit nllr’iDS transistor has resistance of2.5 1:9 and capacitance of 0.7 fF, and the pMOS has twice the resistance. Use the data from Figure 6.12. Con
sider both minimum pitch and doublepitch [twice minimum width and spacing) wires. Assume solid metal above and below the wires and that the neighbors are not
switching. 6.? Compute the results with a spreadsheet D =(2 NE) arcnrzsmnos +1 .4J’F]‘ Characteristic velocity of repeated wires Example 5.3 A lﬂxmﬂt—sizedinverterdrivesahimrerterattheeudufthel cumwireﬁumEnm—
Pie 6.1. Suppose thatwire capadunce is {1.2 fFfﬂmandﬂlat unit—sized 1119105 nannie—
turhaeR=IDkﬂ and [7:111 fF. Estimatethe propagation delayuaingtheEhuure
delaymodehneglectdiﬂ'uaiuncapacitance. SIILLI'I'IEIH: Thedrherhas areeietauceefl liﬂ.The receiver haeaZ—urﬁt HMDS nannie— tur and a 4unit pMDS hancistur. fer a capacitance ufﬂﬁ E". The wire capacitance is 21]] EF'.
Figure 6.14 shew: an equivalent circuit fer the system using a single—segment I—mﬂdd.ﬂeEhuamdelayietrd=ﬂﬂﬂﬂlﬂﬂm+ﬂﬂmﬂ+ﬂﬂﬂ ﬂIlth+
ﬂﬁfﬁ=231peTbempadunmufﬂlehngwkedumiuateeﬂ1edelaﬁﬂlempmimum
ufthehiuvezmrisnegligibieincumpmimn. em 5::
men EWﬂimﬂfF EﬂﬁfF
[river Wre Luau FIGURE 5.14 Equlvalant clrcult fer example Example 5.3 Eachwiminapairnfl mullineshascapacitanceufﬂﬂﬂfFJ'rumtcrgInund311110.117!fFaIf
ymtuitsnaighbDLEarhﬁneisdIhmhyanmtEitﬁwiﬂlalkﬂeﬂ'ecﬁuemaiﬂance.
Eaﬁmate ﬁle contalzrljnaﬁnn and pmpagatinn delays of the paﬂl. Negiact parasitic
capadtanmnftheixmrterandreaistanm nfﬂmwirea. SDLUIIDH:WE ﬁnd cpl: {ac3 memmnm mm] = an {F and adj = 1m {Em {Ida}?
'15 RG23: The contamination delay is the minimum Possible delay, whiﬂl m whim
baﬂlwhesawitchhﬂlesamedhacﬁmlnthatcmﬂﬂ=ﬂgdmdﬂmddayisrd=
[l kﬂﬂﬂﬁﬂ FF}: BU paThe pmpagaﬁundﬂayhﬁmmmumm Fumble delaﬁwhich
mﬂmbothwhtsswitﬂthuppnsitedimcﬁmlnthiscmﬂlﬁ= and+lciﬁ
and the dﬁlﬂf in IN: [1 kﬂHDﬁE FF] = 310 P5. This is a factor nffuu: diﬂ‘hrence
betwmlbestandwnmtcaae. Example E.” The path in Figure 6.34 centains amediuru—iengthwire mudeled as alumped {Hyaci
tauce.Writeanequa1iunihrpathdeiayiutermsufxandyHmrlargeshauldﬂiexand
yins'erlers heﬁarshurtestpadl delay? Whatis'lhe stageeﬂert ei'each stage? Tﬂl'F I y 15011: llﬂﬂfF
E 3 FIGURE 5.34 Path saith rnerllumlmgll'l wlre
SﬂLUTIDH: Frum the Logical Eﬁhrt delay made], we ﬁnd the path delay is d=i+j+5ﬂ+E+P {Mill
H] .1: y Diﬂhrenliating ‘With respect te each size and setling the results to I] allmrs us te salve
EQIEAI] ferx=33fF andy: 5? fF. %_ if“ =D=a x3=1ey+5m
{6.41}
l—1—1=D=ry3=lmx
.1: J" The stage eﬂiarts are {sails} = 3.3, [5? + SW33 = 3.2, and {isms} = 1.3. Netiee
that'lhe ﬁrsttwestage eﬂhrts areequal asusuaLhutﬂie third stage eH'hrt isluwecr. As :I:
alreadydrives aiargewire capacitanceymayhe ratherlarge [andisillhearasmall stage
effort} hefcre the incremental increase in delay ef' : driving y equals the incremental
decreases in delay efy driving the autput. Example 5.4 Find the RC ﬂight lime per turn2 for a wire using the Parameters ﬁhm Example 6.3.
Fumress Hie result in Fﬂnﬂmmg, ifthe F04 inverter delay is 15 pa. “flint is the ﬂight
time te mess a 113! mm die? SDLUTIDH: R = Elli} Wmm. ﬂ' = '03.. pFa’rnm. The ﬂight lime is RUE = ED Pse'mIng, er
5.3 Wm2.1he ﬂightlime across a 1'0an dieis thus 5311m4,which is dozens at cluclrcycles. Example 5.5 FigureEJS models agate drivingwires to tmdestinsﬁnns.'1he gate is represented as
aveltsge salute wiﬂ] eEeeﬁve resistance RP'The twnr receivers are located at nndes 3
1nd 4. The wire to node 3 is lung eneugh that it is represented 1with a Fair at
fur—segments, while the wire tn nude 4 is represented wiﬂ: a single segment. Find the
Elmore delayﬁnrn mputxtneaﬂlreeeiver. SDlUllﬂﬂxThe Ehnme delays are
Tug =R1c1 +(e +Rzle+ist+e+efle+se {£13}
Tn; = RIC: + R1032 +C3]+(R1 + Elli1'4 {a} {'3'}
FIGURE 5.15 Interennnest nuﬂellngwiﬂ'l Rﬁt'ee Diﬂisrerrtiaﬁng EQ'EEEE} 1I.Iii1:h respect to N and H" shows ﬂ1at die best length onire
between repeaters is [see Exercise 6.5] is M {15.21}
N "' 3?.ch Recall From Example 4.10 ﬁrst the delay ofao F04 inverter is ERIC. Assumiogﬁm= ﬂ.5
using Folded harrsistors, EQIIEJT] simpliﬁes to ire—ll” m N Race
The delay per urrit length ofa properly repeated wire is %=[2+1i2{1+pm]]1lllfiﬂiwﬂw =1.s?..F04chu {6391 To achieve this delay the inverters should use an nilIDS transistor widlir of RE
If g '5 {fl3”]
Hall: The energy per unit length to send a hit depends on ﬁre wire and repeater capacitances {6.23} E —~cm+nee{1+sw]scw[1+ 1+?“ 2 r ]F3 =1.s?cm15§ﬂ {15.31} In oﬂrer words, repeaters sized for minimum delay add ET'HII to die energy of an uore—
peated wire. Example 5.1!] llilornpute ﬁre delayper'rom ofarepeebed 1Illrrirein aﬁS ornprocess.ﬁssunreﬂ1ewireis
ooamiddle moﬁnghyer‘mdhashwidﬂr,spacirlg,mdheight,soitsresistaoceis2m
ﬂfmmand capacitanceisﬂl proror.'Ihe FDt'lioverter'delay is 15 psrﬂlsoﬁndthe
repeaterspacingmddriversisetoachievethisdehyandﬂre energyper'hit. SDLUIIDH: Using EQEJJ'J}. the delayis :1” = rem H15 psHEm ﬂfmmHDJ. PFrmm] = 41 Farm {see} Thisdelayis aehievedusing aspacingofﬂﬁinunbetweeorepeeteasandannh’lﬂs
driverwidthoflﬂmo[13ﬂ1unitsiee].'llreenerﬂrpesbitisﬂ.4pjfmm. Example 5.5 Estimate the energyT per unit length to send a hit ofinfnnnatinn {one rising and one
failing lIansitinn] in a CMOE process. SIILIJTIDH: E: [(1.2 prmm] [1.[1' VIE = {1.1 pJIhiti'an Someﬁmes energy in a commu—
nication link is expressed as power per gigahit per second: DJ. mWthps. Example 5.? ConaideramicroprocessoronalﬂrnmxlﬂmrndienmningatiiGHaintheES nrn
prooese.ﬁ layer ofnletalisrouterlnn aﬁﬂnmpitchJ—Iaifoftheavaiiahlewirehaclrs
are useiThe 1Wires have an average acﬁvity factor ofﬂ.l. Determine the power con—
surnedhyﬂaelayerofnleta]. SDLUTIDH: There are [2D mm] 1" [25B urn] = EILD'L'II] tracks ofrnetal acroﬁ the die, of
1.Ilirhich dﬂﬁﬂﬂ are occupied. The wire capacitance is {(1.2 prmmHEl] mmﬂt‘lﬂﬂﬂﬂ harks} = lﬁﬂ BF. The power is {DJEIIEIU IlFHlﬂ VH3 CHI] = 43 w. This is dearly1 a
problem, especially considering that ﬁle chip has more than one layer of metal. The
acﬁvityﬁctorneeds to hemuchlmvertolreep powerunderconh'oL 9.1 9.1 Design a fast 6input OR gate in each of the following circuit families. Sketch an
implementation using two stages of logic (e.g., NOR6 + INV, NOR3 + NANDZ, etc). Label each gate with the width of the pMOS and nMOS transistors. Each input can drive no more than 30 Pl. of transistor width. The output must drive a
60/30 inverter (i.e., an inverter with a 60 FL wide pMOS and 30 3. wide nMOS tran
sistor). Use logical effort to choose the topology and size for least average delay. Estimate this delay using logical effort. When estimating parasitic delays, count
only the difﬁlsion capacitance on the output node. a) static CMOS In each case, B = 1 and H: (60+30)f30 = 3. (a1)INOR3(p= 3)+NAND2(p= 2). G: (7f3)*(4f3)= 2819 F: GBH= 28f3.f=
F"2 =3..05 Seconds’rage size: 90*(4f3)ff= 39. D: 2f+P=11..1 9.4 Design a static CMOS circuit to compute F: {A + BXC + D) with least delay. Each input can present a maximum of 30 3. of transistor width. The output must drive a
load equivalent to 500 FL of transistor width. Choose transistor sizes to achieve least
delay and estimate this delay in 1". 9.4 H = 5001' 30 = 16.7. Consider a two stage design: OR—OR—AND—INVERT + INV. G 2*1 2.P 4+1 5.}? GBH 33.3. f=F1""2=5.77.D=2f+P=1s5 ...
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