14. Flip-Flops

14. Flip-Flops - 7/ Class 14: Digital 2: Flip-Flops...

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Unformatted text preview: 7/ Class 14: Digital 2: Flip-Flops R]_';_V0.Ma.rcl_1 10. meg Tropics.- o Oldixh: three-state; binary numbers (Q‘s-coriiplenient. particularly) - “active—low" signals — last time, saw missile launch example: an easy way to handle active-low signals — another sample task, mixing active-low and active—high signals (group exercise) a New: “HDL"“ logic compilers: a first glimpse —- Verilog: the one we‘ll give most of our time to: powerful. and offering a zillion ways to be wrong. But we‘ll keep your tasks simple — ABEL' obsolescent, but easier to use. and better for some purposes: closer to hardware realities (it ' understands active—low signals. unlike Verilog). We may use it to generate the "glue" logic llml will link your microproeessorlcontroller to its memory and peripherals. - Apply these to the recent active—low exercise. . . rr ABEL makes it really clean: just declare active levels when assigningvariables to pins * Verilog is not so good: klngey re—dertnition (inversion) of active—low signals can help somewhat , «- Flip-Flops -— primitive: 2 versions (transistors; SR with cross-coupled NANDS) — practical: edge—n iggered, cl0cked "D" flip flop (the workhorse general purpose flop) >r “setup time" is the novel. and counter—intuitive concept: inputs must be stable during this time—— just before clock edge I 4 edge—triggering cleanly separates cause (D level) from effect (Q level). No problem tying vaztr back to D, for example — Applicatioris: >z< simplest: just save a level >t leldC-by‘lwo (frequency): lie QAbar back to D an extend this notions to (livide-by—l'our - simplest: ripple counter - better: S's-'itchmnoutr counter — (iftimc): shift register (even simpler than a counter) “Hardware lf)escr1;:ition Language. +Raflflual' "Brand 33 . CL 1 Active-Low, again '77:) wit {0 mmmr mg as “nomh‘k/ sugacsfil‘i “aft 109.172. is China-$9M, “MIA of tIAJELITE [as A agnu m 2:; ‘agsew 73a mammafir "burl ' 0 WHITE. VALID and TIApr all are asserted. 1.1 Diagram it with Gates Draw gates that will. . . lAssen ‘DOI‘T 1r. .. — so long as neither PROTECTED nor BLOCK is asscrtcd; \ 0 or if either WILLY or NII {/fl ' WRITE o————O ______r__d____._ _fl_____fi___flflfflr#”"—_fi—‘““~a wxuxrjijfi ‘~ ) ’l‘lMED 0 U . PROTECTE rm BLOC @ we ling MW w.an WT dfimssarfil 1.2 Do it with alogic compiler: ABEL tn?" “:3 W- / In lhis case. we fnst assign van'ables to PAL pins, and as we assi mam. we state whether they are aetive HIGH (the default) or active LOW (expressed by plac‘ g an exclamation point, read as “bang,” ahead 0fthw1able name): / L .' .I‘T‘E, VALID, !TIMED, EPROTECTED, EDDI'I‘, £BI.OCK. !‘«'-‘ LY, NELLY Qiu l .7; // Bang all signala that are 3: - Ol\ lqnal type: combinaticnal rather thgfl/sequential [no flop L/ H PMTicT‘cb #7 Mel/K) '- //OUTPUTS :DOXT pin 23 ist pe 'com': /f Reiterate default EQUATIONS (Loft) W Ubfiomm ‘32 WW“) 1 4,2496%“) Hr 1.3 Do it with a logic compiler: Verilog module act_loflverilog(write_bar, valid‘ timed_bar, protubar. blockrbar, wiliy_bar, niliy, doiL_ba:]: input, NI' 1 te_bar: input valid; input timed_bar; 1nput prot_ba:; input block_bar; input willy_bar: input Di 1 13:: output dainflbar; wire write_barlvaiid,timed_bar.prct_bar,block_bar,willy_bar.niLly,dciL_barldoit; // specify all inputs and outputs and inhermediate "dGiL“ as ordinary signal (“wire”) // versus the sor: that holds a value ("reg") // Now flip all active-low signals. so we can treat ALL signals as active-high as we write equations assign write = !write_bar; // makes a temporary internal signal (write) nevei assigned to a pin assign timed = Jcimed_bar; assign pro: * Eprmt_bar; “:p assiqn block = lbiockHbar; assign willy = Jwilly_bar; assign doit_bar = Edoit; // this CutpuL logic is reversed because the active-high “d¢it" // will be an input to this logic( used to generate Lhe OUTPUT assign doit T [Lon'ie a-bmé’ 1 DQLJQ SA (mafia 113/002) [ (class. 1 {dailymarl 908.ch; March I9. 2003) endmodule ’31) i s: '5 59 g» \5 \ Mm; ma WW A] Wm \ a DWI/JIM flame—L315!” (3 \\€a,c/Z\ SEW. (Anise mm; Magi mMVe NEL rummma WEEm mo_:w>lo_|8mnxoo_m +Hauonai'3rand ‘. ". T: .g'ii‘ shrug 64m) R‘rflm (used a'kmr' sew Rm‘c} Maw LI Houb ("wemmb") hm infimsfiw (gig (I unnarmarama 7:: 3:11;: .25 :1 512:“ ...
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This note was uploaded on 04/07/2008 for the course PHYSICS 123 taught by Professor Hayes during the Spring '07 term at Harvard.

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14. Flip-Flops - 7/ Class 14: Digital 2: Flip-Flops...

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