CH05 Fixed- Point versus Floating-Point

CH05 Fixed- Point versus Floating-Point - CHAPTER 5...

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C H A P T E R 5 Fixed-Point versus Floating-Point From an arithmetic point of view, there are two ways a DSP system can be implemented in LabVIEW to match its hardware implementation on a processor. These include fixed-point and floating-point implementations. In this chapter, we discuss the issues related to these two hardware implementations. In a fixed-point processor, numbers are represented and manipulated in integer format. In a floating-point processor, in addition to integer arithmetic, floating-point arithmetic can be handled. This means that numbers are represented by the combination of a mantissa (or a fractional part) and an exponent part, and the processor possesses the necessary hardware for manipulating both of these parts. As a result, in general, floating-point processors are slower than fixed-point ones. In a fixed-point processor, one needs to be concerned with the dynamic range of num- bers, since a much narrower range of numbers can be represented in integer format as compared to floating-point format. For most applications, such a concern can be virtually ignored when using a floating-point processor. Consequently, fixed-point processors usually demand more coding effort than do their floating-point counterparts. 5.1 Q-format Number Representation The decimal value of an N -bit 2’s-complement number, B ¼ b N ± 1 b N ± 2 ::: b 1 b 0 ; b i 2f 0 ; 1 g , is given by D ð B Þ¼± b N ± 1 2 N ± 1 þ b N ± 2 2 N ± 2 þ ::: þ b 1 2 1 þ b 0 2 0 (5.1) The 2’s-complement representation allows a processor to perform integer addition and subtraction by using the same hardware. When the unsigned integer repre- sentation is used, the sign bit is treated as an extra bit. This way, only positive numbers can be represented. 123
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There is a limitation of the dynamic range of the foregoing integer representation scheme. For example, in a 16-bit system, it is not possible to represent numbers larger than 2 15 ± 1 ¼ 32767 and smaller than ± 2 15 ¼ ± 32768. To cope with this limitation, numbers are often normalized between –1 and 1. In other words, they are represented as fractions. This normalization is achieved by the programmer moving the implied or imaginary binary point (note that there is no physical memory allocated to this point) as indicated in Figure 5-1 . This way, the fractional value is given by F ð B Þ ¼ ± b N ± 1 2 0 þ b N ± 2 2 ± 1 þ ::: þ b 1 2 ±ð N ± 2 Þ þ b 0 2 ±ð N ± 1 Þ (5.2) This representation scheme is referred to as the Q-format or fractional representa- tion. The programmer needs to keep track of the implied binary point when manipulating Q-format numbers. For instance, let us consider two Q15 format numbers. Each number consists of 1 sign bit plus 15 fractional bits. When these numbers are multiplied, a Q30 format number is generated (the product of two fractions is still a fraction), with bit 31 being the sign bit and bit 32 another sign bit (called an extended sign bit). Assuming a 16-bit wide memory, not enough bits are available to store all 32 bits, and only 16 bits can be stored. It makes sense to store
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