Solution Manual for CMOS Digital Integrated Circuits Analysis and Design 4th Edition by Kang

# Solution Manual for CMOS Digital Integrated Circuits Analysis and Design 4th Edition by Kang

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Exercise Problems 3.1 Consider a MOS system with the following parameters: 18 -3 A 10 2 1.6nm 1.04V N =2.8 10 cm 4 10 C/cm ox GC OX t Q q   a. Determine the threshold voltage V T0 under zero bias at room temperature (T = 300 K). Note that 0 3.97 ox and 0 11.7 si . SOLUTION : First, calculate the Fermi potentials for the p-type substrate and for the n-type polysilicon gate: 10 18 1.45 10 ( ) ln 0.026V ln 0.49V 2.8 10 i F A n kT substrate q N   The depletion region charge density at V SB = 0 is found as follows: 0 19 18 14 7 2 2 2 ( ) 2 1.6 10 (2.8 10 ) 11.7 8.85 10 2 0.49 9.53 10 C/cm B A Si F Q q N substrate            The oxide-interface charge is: 19 10 -2 9 2 1.6 10 C 4 10 cm 6.4 10 C/cm ox ox Q q N The gate oxide capacitance per unit area is calculated using the dielectric constant of silicon dioxide and the oxide thickness t ox . 14 6 2 7 3.97 8.85 10 F/cm 2.2 10 F/cm 1.6 10 cm ox ox ox C t Now, we can combine all components and calculate the threshold voltage. 0 0 2 ( ) 1.04 ( 0.98) ( 0.53) (0.03) 0.44V B ox T GC F ox ox Q Q V substrate C C       b. Determine the type (p-type or n-type) and amount of channel implant (N I /cm 2 ) required to change the threshold voltage to 0.6V

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