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exam2 review - CSE261 Digital Logic Design Spring 2008 Exam...

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Unformatted text preview: CSE261 Digital Logic Design Spring 2008 Exam 2 Review Exam Date: Monday, April 14 2008 Date: Monday, 14, Closed book and notes Blocks Inputs and outputs Data flow paths Bus Block Diagram CSE261 E2 Review 1 Documentation CSE261 E2 Review 2 PLA Example I1'.I2'.I3'.I4' I1.I2 I1.I3' I1'.I3.I4 I2 I1'.I2'.I4' Decoder cascading: 4-to-16 decoder to- Two 3-to-8 3-toO1 = I1.I2 + I1'.I2'.I3'.I4' O2 = I1.I3' + I1'.I3.I4 + I2 O3 = I1.I2 + I1.I3' + I1'.I2'.I4' PLA CSE261 E2 Review 3 Decoders CSE261 E2 Review 4 E2 Exercises 1 CSE261 Digital Logic Design Spring 2008 Implementing the Canonical Sum The binary decoder generates all minterms of n-variable logic function. nThe canonical sum of a logic functions is obtained by adding all minterms of that function: Match the order of input bits Activate Enable inputs 74x148 8-input priority encoder 8- Example: F = X,Y,Z (2,4,7) +5V 74x138 G1 G2A G2B Z Y X A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 F ActiveActive-low I/O EI: Enable Input GO: Got Something EO: Enable Output CSE261 E2 Review 5 Decoders Encoders CSE261 E2 Review 6 8 data sources sharing one line Row 0 1 2 3 4 5 6 7 ThreeThree-state buffers CSE261 E2 Review 7 Multiplexers Example: Functional Decomposition Example Truth Table X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F 0 0 1 0 1 0 0 1 F01(Z) = Z' 0 F10(Z) = Z Z' Z F11(Z) = Z X Y CSE261 E2 Review 8 Decomposed Truth Table Row 0,1 F00(Z) = 0 2,3 4,5 6,7 X 0 0 1 1 Y 0 1 0 1 Z 0 X X X F 0 Z' Z' Z I0 I1 I2 4x1 Y MUX S0 F I3 S1 LSB Multiplexers E2 Exercises 2 CSE261 Digital Logic Design Spring 2008 8 bit Comparator +5V 74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3 A<B A=B A>B Full Adder 1-bit-wide adder, produces sum and carry outputs bitX 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 S = X'Y'CIN+X'YCIN'+XY'CIN'+XYCIN S = X Y CIN COUT = XY + XCIN + YCIN Least Significant bits Most Significant bits Comparators CSE261 E2 Review 9 Adders CSE261 E2 Review 10 Carry Lookahead Logic Ci+1 = gi + pi.Ci gi = Xi.Yi pi = Xi + Yi MSI Arithmetic Logic Units (ALU ) ALU performs Arithmetic and Logical Functions A, B: 4 bit inputs S3, S2, S1, S0: Function select M = 0: Arithmetic operations: + = Plus, = Minus M = 1: Logical operations: + = OR, . = AND 1 L i l ti OR Inputs S3 0 0 1 1 1 S2 0 1 0 0 1 1 S1 0 1 0 1 0 1 S0 0 0 1 1 0 1 Functions M=0 (arithmetic) A 1 + CIN A B 1 + CIN A + B + CIN (A OR B) + CIN A + A + CIN A + CIN M=1 (logic) A' A XOR B' A XOR B A+B 0000 A 74x181 S0 S1 S2 S3 M CIN A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 COUT G P A=B Almos the same amount of delay ost C1 = g0 + p0.C0 C2 =g1 + p1.C1 = g1 + p1g0 + p1.p0.C0 g p C3 = g2 + p2.C2 = g2 + p2.g1 + p2.p1.g0 + p2.p1.p0.C0 C4 = g3 + p3.C3 = g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0 + p2.p1.p0.C0 C5 = ......................................................................................................... X 0,Y 0 X 1,Y 1 ... X N-1,Y N-1 C i,0 P0 C i,1 P1 ... C i,N-1 i,N- P N-1 1 Adders Adders CSE261 E2 Review 11 CSE261 E2 Review 12 E2 Exercises 3 CSE261 Digital Logic Design Spring 2008 The Array Multiplier X3 X2 X1 X0 Y1 Z0 Today's ROMs 256K bytes, 1M byte, or larger Use MOS transistors HA X3 X2 FA X1 FA X0 Y2 HA Z1 FA X3 X2 FA X1 FA X0 Y3 HA Z2 FA Z7 Z6 FA Z5 FA Z4 HA Z3 Multipliers CSE261 E2 Review 13 ROM CSE261 E2 Review 14 ROM control and I/O signals EXERCISES ROM CSE261 E2 Review 15 CSE261 E2 Review 16 E2 Exercises 4 CSE261 Digital Logic Design Spring 2008 Digital Logic Design is truly an "art" of mapping circuit specifications into gate-level realizations. The art is in formulating the problem and gatethe possible solutions based on "chosen" building blocks. In tackling world problems, which mostly seem more like puzzles than any thing having to do with circuit elements, we follow a method with the following steps: Exercise 1: It is required that data from four sources (A, B, C, D) be transmitted to either of the two destinations E and F using a two-bit data bus. Each twodata item is two bits wide (e.g. A0A1, B0B1, etc.). Draw the bus circuit using three-state buffers. (Hint: you need 6 independent control signals, threeControl A, Control B, ..., Control F, and 12 three-state buffers) A B F three- Step 1: Understand the problem, extracting the key points such as problem, inputs/outputs and constraints such as size/cost/power/technology limitations. Step 2: Describe it formally, using representations such as Boolean equations, formally, truth tables, and state diagrams. A0 A1 F0 F1 Ctrl F Step 3: Choose a technology for implementation such as two-level twocombinational networks, PLA/PALs, ROMs, and FPGAs. Ctrl A B0 B1 Ctrl B CSE261 E2 Review 17 CSE261 E2 Review 18 Step 4: Apply the design procedure for the selected implementation approach. Exercise 2: Exercise 3: The figure below shows how 74LS541 can be used as a Microprocessor input port. In the figure, two independent input sources (input Port 1, (input 1, input Port 2) are interfaced to the Microprocessor data bus through the 2) 74LS541 ICs. Assuming the only control signals available from the Microprocessor are the READ, INSEL1, INSEL2, INSEL3 (all active low) as shown. Indicate how this circuit can be expanded to receive user inputs from 8 independent sources (each input source is 8-bit wide) 8- Implement the logic function F(W,X,Y,Z) = (0,3,4,5,10,13,15) using two 3-to-8 line decoders, one inverter, and three OR gates. todecoders, inverter, gates. W X Y Z E 3x8 Decoder G2 of 541 #1 INSEL1 INSEL2 INSEL3 3x8 Decoder G2 of 541 #8 E X Y Z 3x8 Decoder CSE261 E2 Review 19 CSE261 E2 Review 20 E2 Exercises 5 CSE261 Digital Logic Design Spring 2008 Exercise 5: Exercise 7: In the circuit below a 2-to-1 line decoder is connected to a 4x1 Multiplexer 2-toas shown. Complete the truth table for this circuit. Decoder outputs and the enable inputs are active HIGH. +5V +5V Implement the Full Adder using the 74x138 decoder with minimum number of additional logic gates. I0 I1 Y1 Y2 Y3 4x1 MUX B A 2-to-4 toDecoder E Y0 I0 I1 I2 E Y F I3 S1 S0 A 0 0 1 1 B 0 1 0 1 Y3 0 0 0 1 Y2 0 0 1 0 Y1 0 1 0 0 Y0 1 0 0 0 F I0=Y0 1 I1=0 0 I2=Y2' 0 I0=Y0 0 CSE261 E2 Review 21 0 1 2 3 4 5 6 7 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin Ci 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 Cout C t 0 0 0 1 0 Cin 1 B 1 A 1 S SUM(A,B,Cin)= (1,2,4,7) Cout(A,B,Cin)= (3,5,6,7) Cout CSE261 E2 Review 22 Exercise 8: Exercise 4: Implement the function F(A,B,C,D)= (2,3,5,7,8,9,10,13,14,15) using a multiplexer. Use the least significant bit as the data input. I0 I1 2 3 1 I2 4 5 D I3 6 7 D I4 8 9 0 I5 10 11 D' I6 12 13 D I7 14 15 1 Given a four-input Boolean function F(A,B,C,D)= (1,2,4,6,8,9,10,14), fourimplement the function using an 8x1 multiplexer. Use the most significant bit as the data input. F(A,B,C,D)= (0,3,5,7,11,12,13,15) I0 I1 1 9 0 A A' 0 0 1 A 1 0 1 LSB D' D 0 1 0 I2 2 10 0 I3 3 11 1 I4 4 12 A I5 5 13 1 I6 6 14 0 I7 7 15 1 MSB A' A 0 8 A' 0 1 D D 1 D' D 1 8x1 MUX F 8x1 MUX F ABC CSE261 E2 Review 23 BCD CSE261 E2 Review 24 E2 Exercises 6 CSE261 Digital Logic Design Spring 2008 Exercise 13: Exercise 14: Implement the following Boolean function using a multiplexer. F(A,B,C,D)= (1,3,4,6,9,12,14) (Use the MSB variable as the data input) I0 I1 1 9 1 I2 2 10 0 I3 3 11 A' I4 4 12 1 I5 5 13 0 I6 6 14 1 I7 7 15 0 A 4x1 multiplexer has inputs B, C connected to the selection inputs S1 and S0 respectively. The data inputs, I0 through I3, are as follows: I0=I3=0, I1=1, and I2=A, where A is the MSB. Determine the Boolean function that the multiplexer implements. MSB A' A 0 8 0 0 1 A 0 I0 I1 4x1 Y I2 MUX I3 S1 S0 F MSB I0 A' A 0 4 0 I1 1 5 1 I2 2 6 A I3 3 7 0 0 1 0 A' 1 0 1 0 8x1 MUX F F(A,B,C)= (1,5,6) BCD CSE261 E2 Review 25 CSE261 E2 Review 26 Exercise 9: the parallel binary adder module(s), 74x283, and minimum number of logic gates, design a BCD adder circuit to perform the addition of two BCD digits. The Using BCD OPERANDS X3 X2 X1 X0 Y3 Y2 Y1 Y0 Cout S3 S2 S1 S0 Cin BCD addition process is summarized below: Add the BCD digits using ordinary binary addition. If the sum is 9 or less, the sum is in proper BCD form and no correction is necessary When the sum of two digits is greater than 9, or a carry is generated, a correction of 0110 should be added to that sum to produce the proper result. 0 0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 Cout S3 S2 S1 S0 0 Cout BCD SUM CSE261 E2 Review 27 CSE261 E2 Review 28 E2 Exercises 7 CSE261 Digital Logic Design Spring 2008 Exercise 11: Exercise 12: The tristate gates provide an alternative method and often a more economical way of implementing the same capability as a multiplexer. Complete the truth table for the Ex1 MUX (tristate logic shown below). Expand the tristate logic to implement a 4x1 MUX with inputs I0I1I2I3 and select signals S1S0 I0 F I1 SEL 0 1 F I0 I1 Complete the truth table and comment field for the MUX-based logic unit MUXshown below. The logic unit has two data inputs A and B, and three control inputs C2C1C0. I0 I1 B A B A I2 I3 C2 0 0 F C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 F 1 A+B (A+B)' AB (AB) (AB)' (AB)' AB 0 CSE261 E2 Review 30 8x1 I4 MUX I5 I6 I7 C2 C1 C0 LSB 0 0 1 1 1 1 S1 0 select S1 S0 0 1 1 S0 0 1 0 1 F I0 I1 I2 I3 B A CSE261 E2 Review 29 Exercise 5-36: 5Design a decimal decoder in place of a 4-to-16 decoder and compare 4-togate requirements. Y0 = D'C'B'A' Y1 = D'C'B'A Y2 = C'BA' Y3 = C'BA Y4 = CB'A' Y5 = CB'A Y6 = CBA' Y7 = CBA Y8 = DA' Y9 = DA Y8, Y9 require only two inputs, Y2Y2-Y7 require three inputs, and Y0, Y1 require four inputs as before. CSE261 E2 Review 31 Exercise 5-45: 5Design a 10-to-4 encoder with inputs in 1-out-of-10 code and outputs in 10-to1-out-ofBCD. BA DC 0 1 3 2 D 00 0 1 3 2 4 5 7 6 01 4 5 7 6 11 12 d 13 d 15 d 14 d C 8 9 10 8 9 A 00 01 11 B 10 11 d 10 d CSE261 E2 Review 32 E2 Exercises 8 CSE261 Digital Logic Design Spring 2008 Exercises 5-46: 5Draw the logic diagram for a 16-to-4 encoder using just four 8-input NAND 16-to8gates indicating active levels of the inputs and outputs in your design. Exercises 5-54: 5Design a 3-input, 5-bit multiplexer that 35fits in a 24-pin IC package. Write the 24truth table and draw a logic diagram and logic symbol for your multiplexer. Inputs S1 0 0 1 1 S2 0 1 0 1 1Y 1D0 1D1 1D2 0 2Y 2D0 2D1 2D2 0 Outputs 3Y 3D0 3D1 3D2 0 4Y 4D0 4D1 4D2 0 5Y 5D0 5D1 5D2 0 The inputs are active low and the outputs are active high in this design CSE261 E2 Review 33 CSE261 E2 Review 34 Exercises 5-54: 54-to-1 toMultiplexer I0 I1 Y I2 8-to-1 toMultiplexer Determine the maximum propagation delay from any A or B bus input to any F bus output of the 1616-bit CLA shown below. The worst-case delay is the sum of three worstnumbers: 1. 7 ns 33 ns 27 ns I3 In U1U4, the worst-case delay from U1 worstany Ai, Bi to /G or /P (33 ns). In U5, the worst-case delay from any worst/GI or /PI to any CI (7 ns). In U1U4, the worst-case delay from U1 worstCIN to any function output (27 ns). 2. S1 S0 3. Thus, the total worst-case delay is 67 ns. worst- CSE261 E2 Review 35 CSE261 E2 Review 36 E2 Exercises 9 CSE261 Digital Logic Design Spring 2008 Ta bl e 5 - 3 Propagation delay in nanoseconds of selected CMOS and TTL MSI parts. 74HCT Typical Part From To tpLH,tpHL 74AHCT / FCT Typical tpLH, tpHL 74LS Typical tpLH tpHL Maximum tpLH, tpHL Maximum tpLH,tpHL Maximum tpLH tpHL Exercises 5-79: 5Estimate the number of product terms in a minimal sum-of-products sum-ofexpression for the c32 output of a 32-bit binary adder. Be more 32adder. specific than "billions and billions." The function h 65 inputs, and the worst 65-input function ( 65-i Th f ti has i t d th t 65-i tf ti (a 65-input t parity circuit) has 265 1 terms in the minimal sum-of-products expression. sum-ofOur answer can't be any worse than this, but we can do better. c1 has 3 product terms: c1 = c0 x0 + c0 y0 + 0 y0 terms: c2 = c1 x1 + c1 y1 + x1 y1 Substitute c1 in the equation above and "multiply out," 3+3+1=7 3+3+1=7 product terms Let p od ct te ms. L t us assume th t no f th reduction i possible. terms. that further d ti is ibl c3 has 7+7+1=15 product terms 7+7+1=15 product terms. the expression for ci has 2i+1 1 '138 any select any select G2A, G2B G1 '139 '151 '153 '157 '182 any select any select enable any select any select any data any data enable enable any select any data enable select any data enable any Gi, Pi any Gi, Pi any Pi C0 output (2) output (3) output output output (2) output (3) output Y Y Y Y Y Y output output output output output output C13 G P C13 EVEN ODD any Si any Si C4 C4 any Fi G P any Fi any Fi G, P PEQQ PEQQ PGTQ PGTQ '280 '283 any input any input C0 any Ai, Bi C0 any Ai, Bi '381 CIN 23 23 22 22 14 14 11 17 18 16 15 12 15 14 12 11 15 12 12 13 13 11 17 18 19 22 21 19 20 45 45 42 42 43 43 43 51 54 48 45 36 45 43 43 34 46 38 38 41 41 35 50 53 56 66 61 58 60 '682 any Ai, Bi any Ai, Bi any Ai, Bi any select any select any Pi any Qi any Pi any Qi 31 26 26 26 26 32 69 69 69 69 8.1 / 5 13 / 9 11 8.1 / 5 13 / 9 21 7.5 / 4 12 / 8 12 7.1 / 4 11.5 / 8 14 6.5 / 5 10.5 / 9 13 6.5 / 5 10.5 / 9 18 5.9 / 5 9.5 / 9 16 -/5 -/9 27 -/5 -/9 14 -/4 -/7 20 -/4 -/7 13 -/4 -/7 26 -/4 -/7 15 -/5 -/9 19 -/4 -/7 10 -/4 -/7 16 6.8/7 11.5/10.5 15 18 5.6 / 4 9.5 / 6 9 7.1/7 12.0/10.5 13 14 4.5 5 4.5 6.5 -/6 - / 10 33 -/6 - / 10 23 16 15 11 11 18 14 27 20 21 30 21 20 35 34 53 47 48 -/7 - / 11 13 -/7 - / 11 14 -/9 - / 14 20 -/9 - / 14 21 18 20 20 13 22 25 21 18 20 16 12 20 18 25 17 21 23 9 21 4.5 7 6.5 7 29 31 15 15 11 12 21 33 33 15 51 15 15 15 19 20 27 18 26 20 29 24 43 23 32 21 42 24 29 15 24 27 14 23 7 7.5 6.5 10 50 35 24 24 17 17 41 39 32 38 33 38 32 30 32 26 20 32 30 38 26 32 14 7 10.5 10 10.5 45 50 24 24 22 17 23 30 33 23 25 25 30 30 25 25 30 CSE261 30 Thus, the number of terms in a sum-of-products expression for c32 is no sum-ofmore than 233 1, fewer if minimization is possible. E2 Review 37 CSE261 E2 Review 38 Indicate whether the following two MUX circuits implement the following truth table. Design a circuit that can add or subtract two 3-bit binary numbers 3using 2's complement. It must also generate carry out and overflow signals. You can use one-bit full adders, MUXs, decoders, and any oneother logic gates in your design. A 0 1 2 3 4 5 6 7 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 1 0 0 1 1 0 1 1 C' C C' 1 0 1 4x1 2 MUX 3 S0 S1 AB 0 1 A' A 0 1 4x1 2 MUX 3 S0 S1 BC Cout Overflow CTRL: 0 Add, 1 Subtract A2 A1 A0 B2 B1 B0 0 0 0 0 1 1 1 1 Cin S2 S1 S0 CSE261 E2 Review 39 CSE261 E2 Review 40 E2 Exercises 10 CSE261 Digital Logic Design Spring 2008 Design a circuit that adds two 5-bit binary numbers. You can only use one 54-bit full adder, one AND gate, and one XOR gate in your design. x4 x3 x2 x1 x0 y4 y3 y2 y1 y0 Cout s4 s3 s2 s1 s0 Design a circuit that outputs a 1 when the sum of two 4-bit unsigned 4binary numbers is: greater than 9 AND less than or equal to 15. You can use a 4-bit full adder and any other logic gate. 4- A3 A2 A1 A0 Cout A3 A2 A1 A0 Cout B3 B2 B1 B0 Cin B3 B2 B1 B0 Cin 4-bit Adder S3 S2 S1 S0 4-bit Adder S3 S2 S1 S0 CSE261 E2 Review 41 CSE261 E2 Review 42 E2 Exercises 11 ...
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