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designexample2 - CSE261 ` FSM 1 2-bit up-down counter (2...

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Unformatted text preview: CSE261 ` FSM 1 2-bit up-down counter (2 inputs) direction: D = 0 for up, D = 1 for down count: C = 0 for hold, C = 1 for count S1 S0 C D N1 N0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 C=0 D=X C=0 D=X C=0 D=X C=0 D=X C=1 D=0 C=1 D=0 C=1 D=0 C=1 D=0 C=1 D=1 N1 = CS1 + CDS0S1 + CDS0S1 + CDS0S1 + CDS0S1 = CS1 + C(D(S1 S0) + D(S1 S0)) N0 = CS0 + CS0 0 1 1 0 1 1 0 1 0 0 1 1 0 0 1 D S1 S0 C 0 1 1 0 1 1 0 1 0 0 1 1 0 0 1 D S1 S0 C 0 1 1 0 1 1 0 1 0 0 1 1 0 0 1 D S1 S0 C 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 D S1 S0 C 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 D S1 S0 C 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 D S1 S0 C CSE261 ` FSM 2 Mealy machines tend to have less states different outputs on arcs (n2) rather than states (n) Moore machines are safer to use outputs change at clock edge (always one cycle later) in Mealy machines, input change can cause output change as soon as logic is done...
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This note was uploaded on 05/08/2008 for the course CSE 261 taught by Professor Ercanli during the Spring '08 term at Syracuse.

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designexample2 - CSE261 ` FSM 1 2-bit up-down counter (2...

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