design practice

# design practice - CSE261 April 2008 Sequential Logic Design...

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CSE261 April 2008 Sequential Circuit Practices 1 1 Synchronous System Timing Latches, Flip-flops, and Registers Counters Shift Registers Sequential Logic Design Practices 2 t ffpd t comb t setup & t hold t ffpd - CLK to Q, FF propagation delay (min, max) t comb - combinational logic delay (min, max) t setup - input stable before clock (min) t hold - input stable after clock (min) Synchronous System - Detailed Timing Latches, Flip-flops, and Registers CLK DQ Combinational Logic 3 t ffpd Flip-Flop outputs Clock t H t L clk t setup-time margin t setup t hold Flip-Flop inputs Combinational outputs comb t Synchronous System - Detailed Timing Latches, Flip-flops, and Registers C. L. 4 t clk,min > t ffpd,max + t comb,max + t setup,min Difference Æ Setup time margin t ffpd, min + t comb,min > t hold,min Difference Æ Hold time margin Synchronous System - Detailed Timing Latches, Flip-flops, and Registers C. L. Required

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CSE261 April 2008 Sequential Circuit Practices 2 5 Max Frequency: t clk,min 40 ns Æ f max 25 MHz Synchronous System Example Latches, Flip-flops, and Registers Memory Combinational Logic t comb = 2 ns, min and 20 ns, max t ffpd = 3 ns, min and 15 ns, max t setup = 5 ns, min t hold = 2 ns, min At 10 MHz clk Setup margin: 100 - (15 + 20 + 5) = 60 ns Hold Margin: (3 + 2) -2 = 3ns Setup Margin: t clk,min > t ffpd,max + t comb,max + t setup,min Hold Time Margin: t ffpd, min + t comb,min > t hold,min 6 Latches, Flip-flops, and Registers 74x175: Multibit registers and latches 1 1 1 0 7 Latches, Flip-flops, and Registers 74x373: Octal latch Latch : output follows input when G is asserted Output enable Latch-enable input “C” 00111 1 1 0 8 Latches, Flip-flops, and Registers 74x374: Octal register Register : edge-triggered behavior 1 1 0
CSE261 April 2008 Sequential Circuit Practices 3 9 Counters Counters EN EN EN EN EN EN S1 EN’ S2 EN’ S3 EN’ S4 EN’ RESET S5 EN’ S6 EN’ Clocked sequential circuit with single-cycle state diagram Modulo-m counter = Divide -by-m counter 10 LSB MSB Counters Synchronous counter: Serial enable logic Flip-flops enabled when all lower flip- flops = 1. Enable propagates serially — limits speed. Requires: (n-1) Δ t < T CLK All flip-flop outputs change simultaneously t CQ after CLK Most Frequently Used Type of Counter 11 Counters Synchronous counter: Parallel enable logic Single-level enable logic per flip-flop Fastest and most complex type of counter. Requires Δ t < T CLK All outputs change simultaneously t CQ after CLK LSB MSB 12 74x163 4-bit counter Counters

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CSE261 April 2008 Sequential Circuit Practices 4 13 74x163 Counters 14 Counters CLK +5 V 0, 1, 2, 3, 4, …, 15, 0, 1, … Counter Application-1: Free Running Modulo-16 Counter 15 Divide-by-16 ” counter Counters Counter Application-1: 16 Counters Load
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• Spring '08
• Ercanli
• Metastability in electronics, Flip-flop, Chaney Chaney Chaney Chaney Chaney Chaney Chaney Chaney, Sequential Circuit Practices, tffpd

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design practice - CSE261 April 2008 Sequential Logic Design...

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