Lect 7 - CSE 261 Spring 2008 A Generic Digital Processor Building Blocks for Digital Architectures RAM ROM Buffers Shift registers Bit-Sliced

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Unformatted text preview: CSE 261 Spring 2008 A Generic Digital Processor Building Blocks for Digital Architectures RAM, ROM, Buffers, Shift registers Bit-Sliced Design BitControl INPUT - OUTPUT MEMORY CPU Bit 3 Multiplexer Register Shifter Adder CONTROL DATAPATH Finite state machine: PLA, Counters, ... Bit 2 Bit 1 Bit 0 Tile identical processing elements Interconnect: Switches, Arbiters, Bus, ... Arithmetic Unit: Adder, multiplier, shifter, comparator, ... ALU Components C5 1 ALU Components C5 DATADATA -OUT 2 ALU Components C5 4 DATADATA -IN Comparators Compares Two binary words and indicate if they are equal 1. 2. 3. 4. Comparators Adders Multipliers Read-only memories (ROMs) Read- A Comparator B A=B Advanced Comparators: A A=B Comparator B A>B A<B 1-bit Comparator: XOR gate , the Output is 1 if A B A B ALU Components C5 3 F Comparators CPU Design 1 CSE 261 Spring 2008 Equality Comparators 1-bit comparator Iterative Comparator EQI 0 1 1 1 1 X Y X X 0 0 1 1 Y X 0 1 0 1 EQO 0 1 0 0 1 1 bit comparator: 4-bit comparator EQ_L EQI Comparators ALU Components C5 5 EQO Comparators ALU Components C5 6 Multibit Iterative Comparator Iterative Comparator: cascaded 1 bit comparators X0 Y0 X1 Y1 X(N-1) Y(N-1) X(NY(N- MSI Comparator: 74x85 4 bit comparator 3 Cascading inputs Cascading inputs initial values: (A=B IN) = 1 IN) EQN 74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3 (A<B)+(A=B).(A<B IN) (A<B)+(A=B).(A<B IN) (A=B).(A=B IN) (A=B).(A=B IN) (A>B)+(A=B).(A>B IN) (A>B)+(A=B).(A>B IN) X EQ0 =1 EQI Y EQ1 EQO X EQI Y EQ1 EQO EQ1(N-1) EQ1(N- X EQI Y EQO (A>B IN) = 0 IN) (A<B IN) = 0 IN) Comparators ALU Components C5 7 Comparators ALU Components C5 8 CPU Design 2 CSE 261 Spring 2008 8 bit Comparator +5V 74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3 A<B A=B A>B Half Adder X 0 0 1 1 Y 0 1 0 1 SUM 0 1 1 0 CO 0 0 0 1 X Y CO S SUM = X Y CO = X.Y Least Significant bits Most Significant bits Comparators ALU Components C5 9 Adders ALU Components C5 10 Full Adder 1-bit-wide adder, produces sum and carry outputs bitX 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full-Adder circuit FullS = X Y CIN COUT = XY + XCIN + YCIN S = X'Y'CIN+X'YCIN'+XY'CIN'+XYCIN +X' +XY' S = X Y CIN COUT = XY + XCIN + YCIN Adders ALU Components C5 11 Adders ALU Components C5 12 CPU Design 3 CSE 261 Spring 2008 Ripple adder Cascade n Full Adders to get n-bit binary Adder Subtraction Subtraction is the same as addition of the two's complement. two' The two's complement is the bit-by-bit complement plus 1. two' bit- byX Y = X + Y' + 1 Y' Speed limited by carry chain: tadder (n-1)tcarry + tsum (nGoal: Make the fastest possible carry path circuit Faster adders eliminate or limit carry chain 2-level AND-OR logic AND2n product terms 3 or 4 levels of logic, carry lookahead Adders ALU Components C5 13 Complement Y inputs to adder, set Cin to 1. For a borrow, set Cin to 0. X Y' 1 Subtraction ALU Components C5 14 Full subtractor = full adder, almost Adder/Subtractor Circuit X(n-1) Y(n-1) X(nY(nX1 Y1 X0 Y0 M COUT/ BOUT X COUT S Y CIN X COUT S Y CIN X COUT S Y CIN S(n-1) / D(n-1) S(nD(n- S1/D1 S0/D0 M = 0: Ripple Adder M = 1: Ripple Subtractor Subtraction ALU Components C5 15 Subtraction ALU Components C5 16 CPU Design 4 CSE 261 Spring 2008 Carry Lookahead Adder Full Adder vs. Carry Lookahead Adder X(n-1) Y(n-1) X(nY(nX S S(n-1) S(nY CLL I(n-1) I(n- X1 X S Y1 Y CLL I1 X0 X S Y0 Y CLL I0 Xi Yi Ci S Xi Yi hsi S COUT Xi-1 XiCi+1 X0 Yi-1 YiY0 C0 Carry Lookahead Logic Ci S1 S0 CLL: Carry Lookahead Logic Carry Lookahead Adder Units Adder ALU Components C5 17 Adder ALU Components C5 18 Carry Lookahead Logic Almost the same amount of delay We need to provide an expression for the ci in the CLL Unit When does the Full adder produce carry? Answer: If both Xi and Yi equal 1 (carry is generated) generated) OR.. If Ci=1 and either Xi or Yi equal 1 (carry is propagated) propagated) Ci+1= (Xi.Yi) + (Xi+Yi).Ci {Compare to: COUT=XY + XCIN + YCIN} (X (X Let gi = Xi.Yi pi = Xi + Yi Generate Propagate Carry Lookahead Logic Ci+1 = gi + pi.Ci C1 = g0 + p0.C0 C2 =g1 + p1.C1 = g1 + p1g0 + p1.p0.C0 C3 = g2 + p2.C2 = g2 + p2.g1 + p2.p1.g0 + p2.p1.p0.C0 C4 = g3 + p3.C3 = g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0 + p2.p1.p0.C0 C5 = ......................................................................................................... X 0,Y 0 X 1,Y 1 ... X N-1,Y N-1 gi = Xi.Yi pi = Xi + Yi Ci+1 = gi + pi.Ci C i,0 P0 C i,1 P1 ... C i,N-1 i,N- P N-1 Adder ALU Components C5 19 Adder ALU Components C5 20 CPU Design 5 CSE 261 Spring 2008 74x283 4-bit adder Uses Carry Lookahead internally 74x283 C0 A0 B0 A1 B1 A2 B2 A3 B3 S0 S1 S2 S3 C4 "generate" generate" "half sum" sum" "propagate" propagate" carry-in from carryprevious stage ALU Components C5 22 Adder ALU Components C5 21 Adder Lookahead carry between groups Ripple carry between groups Adder ALU Components C5 23 Adder ALU Components C5 24 CPU Design 6 CSE 261 Spring 2008 MSI Arithmetic Logic Units (ALU ) ALU performs Arithmetic and Logical Functions A, B: 4 bit inputs S3, S2, S1, S0: Function select M = 0: Arithmetic operations: + = Plus, = Minus M = 1: Logical operations: + = OR, . = AND Inputs S3 0 0 1 1 1 1 Adder 74x181 S0 S1 S2 S3 M CIN A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 COUT G P A=B Binary Multiplication 1 0 1 0 1 0 x 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 + 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 25 Functions S0 0 0 1 1 0 1 M=0 (arithmetic) A 1 + CIN A B 1 + CIN A + B + CIN (A OR B) + CIN A + A + CIN A + CIN M=1 (logic) A' A XOR B' B' A XOR B A+B 0000 A S2 0 1 0 0 1 1 S1 0 1 0 1 0 1 AND operation Partial Products ALU Components C5 Multiplier ALU Components C5 26 Multipliers 8x8 multiplier The Array Multiplier X3 X2 X1 X0 Y1 Z0 HA X3 X2 FA X1 FA X0 Y2 HA Z1 FA X3 X2 FA X1 FA X0 Y3 HA Z2 FA Z7 Z6 FA Z5 FA Z4 HA Z3 Multiplier ALU Components C5 27 Multiplier ALU Components C5 28 CPU Design 7 CSE 261 Spring 2008 Carry-Save Multiplier CarryHA HA HA HA Full-adder array Full- HA FA FA FA HA FA FA FA HA FA FA HA Vector Merging Adder Multiplier ALU Components C5 29 Multiplier ALU Components C5 30 Faster carry chain 80.0 Design as a Trade-Off Tradestatic 60.0 t p (nsec) mirror manchester bypass Area (mm2 ) 0.4 static bypass mirror manchester 0.0 0 10 N 20 look-ahead select 40.0 select look-ahead 0.2 20.0 0.0 0 10 N 20 Multiplier ALU Components C5 31 ALU Components C5 32 CPU Design 8 CSE 261 Spring 2008 Read-Only Memories ReadProgram storage Boot Why `ROM'? ROM' ROM for personal computers application storage for embedded systems. Complete Actually, a ROM is a combinational circuit, basically a truth-table lookup. circuit, truthlookup. Can perform any combinational logic function inputs = function inputs Address Data outputs = function outputs ROM ALU Components C5 33 ROM ALU Components C5 34 Logic-in-ROM example Logic- in- 4x4 multiplier example ROM ALU Components C5 35 ROM ALU Components C5 36 CPU Design 9 CSE 261 Spring 2008 Internal ROM structure Two-dimensional decoding Two- PDP-11 boot ROM PDP(64 words, 1024 diodes) ROM ALU Components C5 37 ROM ALU Components C5 38 Larger example, 32Kx8 ROM Today's ROMs Today' 256K bytes, 1M byte, or larger Use MOS transistors ROM ALU Components C5 39 ROM ALU Components C5 40 CPU Design 10 CSE 261 Spring 2008 EEPROMs, Flash PROMs EEPROMs, Typical commercial EEPROMs Programmable and erasable using floating-gate floatingMOS transistors EEPROM ALU Components C5 41 ALU Components C5 42 EEPROM programming Apply a higher voltage to force bit change Microprocessor EPROM application e.g., VPP = 12 V On-chip high-voltage "charge pump" in newer chips Onhighpump" Erase bits Byte-byte ByteOne block (typically 32K - 66K bytes) at a time Entire chip (`flash') (` flash' Programming and erasing are a lot slower than reading (milliseconds vs. 10's of nanoseconds) 10' ALU Components C5 43 ALU Components C5 44 CPU Design 11 CSE 261 Spring 2008 ROM control and I/O signals ROM timing ALU Components C5 45 ALU Components C5 46 SUMMARY Documentation Standards: Gate symbols, Signals Active Levels, Block diagram, Schematic Diagram, Timing Diagram. 7. 8. SUMMARY Comparators: Parallel Comparators, Iterative Comparators, Cascading Comparators. Adders: Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder / Subtractor Unit, Carry Lookahead Adder, Group-Ripple GroupAdder, Design Choices. Arithmetic Logic Units Multipliers: Binary Multiplication, Array Multiplier, Carry-Save CarryMultiplier. ROM: Implementing Logic Functions, Multiplier, EERPOM, Flash PROMS. Combinational Logic design Structures: 1. Decoders: Binary Decoders, Cascading decoders, Implementing Logic Functions, Seven-Segment Decoders. SevenEncoders: Binary Encoder, Priority Encoder, Cascading Encoders, Encoder applications. Three State Buffers: Octal Three-state Transceiver ThreeMultiplexers: MUX operation, Expanding MUXs, Implementing Logic MUXs, Function Demultiplexers: MUX/DMUX operation, Using Decoders as Demultiplexers: Demultiplexers. Demultiplexers. XOR and XNOR Gates: Logic Symbols, Equivalent Symbols, Parity Circuits using XOR gate, Parity Circuit application ALU Components C5 47 2. 3. 4. 9. 10. 11. 5. 6. ALU Components C5 48 CPU Design 12 CSE 261 Spring 2008 Next time Sequential circuits ALU Components C5 49 CPU Design 13 ...
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This note was uploaded on 05/08/2008 for the course CSE 261 taught by Professor Ercanli during the Spring '08 term at Syracuse.

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