lect5 - CSE261 Spring 2008 Combinational Logic Design...

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Unformatted text preview: CSE261 Spring 2008 Combinational Logic Design Practices 1. 2. 3. Documentation Standards Block diagrams first Documentation Standards Programmable Logic Devices Combinational Logic Design Structures Decoders and Encoders Three-State Buffers Three Multiplexers and Demultiplexers Exclusive OR Gates and Comparators Adders and Subtracters Arithmetic Logic Units (ALUs) (ALUs) 1 Documentation step in hierarchical design Schematic diagrams HDL programs (ABEL, Verilog, VHDL) Timing diagrams Circuit descriptions 2 Block Diagram The building blocks and their function names Schematic diagrams Details of component inputs, outputs, and interconnections inputs, outputs, Pin numbers all inputs and outputs Title blocks Names for all signals data flow paths (the logic signals) bus: related logic signals bus: combined together and drawn with a double or heavy line. Documentation 3 Page-to-page connectors Page- to- Documentation 4 Combinational Logic Practices 1 CSE261 Spring 2008 Example schematic Schematic diagram/Logic Diagram Logic Diagram /A F /B Schematic Diagram 74LS04 74LS00 /A /B 1 3 2 U2 4 1 2 4 3 U1 74LS00 74LS00 10 9 8 F U1 74LS04U2 6 U1 5 Documentation 5 Documentation 6 Flat schematic structure Hierarchical schematic structure Documentation 7 Documentation 8 Combinational Logic Practices 2 CSE261 Spring 2008 Other Documentation Timing diagrams Output Gate symbols from simulator timing-diagram drawing tools timing- Specialized Circuit descriptions Text Can (word processing) be as big as a book (e.g., typical Cisco ASIC descriptions) Typically incorporate other elements (block diagrams, timing diagrams, etc.) Documentation 9 Documentation 10 DeMorgan equivalent symbols Signal names and active levels Signal names are chosen to be descriptive. Active levels: HIGH or LOW named condition or action occurs in either the HIGH or the LOW state, according to the active-level activedesignation in the name. Which symbol to use? Answer depends on signal names and active levels. levels. Documentation 11 Documentation 12 Combinational Logic Practices 3 CSE261 Spring 2008 Example HIGH when error occurs Logic Circuit ERROR Active Levels for Pins In logic gates and logic structures the inversion bubble indicates the active level of the signal Examples: 2-to-4 Decoder to- LOW when error occurs Logic Circuit ERROR_L ERROR active low active high /EN A B EN A B Y0 Y1 Y2 Y3 /Y0 /Y1 /Y2 /Y3 active low ERROR1_L Documentation 13 Documentation 14 Bubble-to-Bubble Logic Design Bubble- toRules: Rules: The active level of the output signal of a logic device should match the active level of the device's output pin. device' pin. ERROR READY ERROR /READY OVERFLOW ERROR Bubble-to-Bubble Logic Design Bubble- toPurpose: To make it easy to understand the function of Purpose: the Logic circuit / HALT / FAIL ERROR / OVERFLOW The active level of the input signal of a logic device should match the active level of the device's input pin. device' pin. REQUEST / ENABLE REQUEST ENABLE / FAIL / OVERFLOW ERROR / FAIL / OVERFLOW ERROR 15 Documentation 16 Documentation Combinational Logic Practices 4 CSE261 Spring 2008 Drawing Layouts Inputs to the left, outputs to the right. Signals flow from left to right. left IN /ENABLE Timing Diagrams Logic Circuit OUT /ENABLE IN Crossing lines/Connected lines (T-type connection) (T- Buses should be named: DATA[0-7], CONTROL DATA[0A signal extracted from a bus should be named DATA5 DATA6 DATA[0-7] DATA[0- Delay depends on Internal circuit structure Logic Family type Source Voltage Temperature OUT tOUT Broken signal paths should be flagged to indicate the source or destination and direction. Bus Flags: Documentation /ENABLE IN OUT Unidirection Bidirection 17 tOUTmin tOUTmax 18 Timing Diagrams Timing Diagram for Data signals (Bus) IN / WRITE Logic Circuit (Memory) Memory) OUT Propagation Delay The delay time between input transitions and the output transitions transitions due to the propagation delay of the the logic gates tp of a signal depends on the signal path inside the logic circuit To find tp for a signal, add the propagation delays of all gates along the path of the signal / WRITE IN OUT old data t2 t3 t1 new data new data For a logic gate tpLH may not equal tpHL pHL tp is specified in the manufacturer data sheets of the IC's IC' t4 Example: t hold 74LS00 74ACT00 19 Timing Diagrams Typical (ns) Maximum (ns) tpLH 9 5.5 t OUTmax tpHL 10 4.0 tpLH 15 9.5 tpHL 15 8.0 20 t setup Timing Diagrams t OUTmin Combinational Logic Practices 5 CSE261 Spring 2008 Programmable Logic Arrays (PLAs) Any combinational logic function can be realized as a sum of products. products. Idea: Build a large AND-OR array with lots of inputs and product Idea: ANDterms, and programmable connections. n Example: 4x3 PLA, 6 product terms n inputs p AND gates inputs AND gates have 2n inputs -true and complement of each variable m outputs m outputs, driven by large OR gates Each AND gate is programmably connected to each output's OR gate output' p AND gates (p << 2n) 21 Programmable Logic Arrays 22 Programmable Logic Arrays Compact representation I1'.I2'.I3'.I4' I1' .I2' .I3' .I4' I1.I2 Some product terms I1'.I3.I4 I1' I2 I1'.I2'.I4' I1' .I2' .I4' I1.I3' I1.I3' O1 = I1.I2 + I1'.I2'.I3'.I4' I1' .I2' .I3' .I4' O2 = I1.I3' + I1'.I3.I4 + I2 I1.I3' I1' Actually, closer to physical layout (`wired logic') (` logic' Programmable Logic Arrays 23 Programmable Logic Arrays O3 = I1.I2 + I1.I3' + I1'.I2'.I4' I1.I3' I1' .I2' .I4' 24 Combinational Logic Practices 6 CSE261 Spring 2008 PLA Electrical Design Programmable Array Logic (PALs) (PALs) How beneficial is product sharing? Not enough to justify the extra AND array PALs fixed OR array Example: PAL16L8 Programmable Logic Arrays 25 Programmable Array Logic 26 7 ANDs per output and 1 AND for 3-state enable 3- 8 outputs 6 outputs available as inputs Decoders Converts input code words into output code words. One-to-One mapping: Each input code One- toproduces only one output code. Binary Code, Gray Code, BCD Code, Any Code! 10 primary inputs Note inversion on outputs output is complement of sum-of-products sum- of newer PALs have selectable inversion Programmable Array Logic 27 Decoders Typically n inputs, 2n outputs: 2-to-4, 3-to-8, 4-to-16, etc. inputs, outputs: 2- to- 3- to- 4- to28 Combinational Logic Practices 7 CSE261 Spring 2008 Binary 2-to-4 decoder ton-to-2n decoder: n inputs and 2n outputs. to- decoder: 2-to-4-decoder logic diagram to- Example: 2-to-4 decoder toInputs EN I1 I0 Y3 Outputs Y2 Y1 Y0 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 Binary Code out- of1-out -of -2n X: don't care don' One output is asserted for each input code. Decoders 29 Decoders 30 MSI Decoder Active Low Enable Active Low outputs Complete 74x139 Decoder Input buffering NAND gates less load faster Inputs /G B A Outputs /Y3 /Y2 /Y1 /Y0 1 0 0 0 0 Decoders X 0 0 1 1 X 0 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 31 Decoders 32 Combinational Logic Practices 8 CSE261 Spring 2008 74x138 3-to-8 decoder to/G1 /G2A /G2B 74x138 3-to-8-truth table toInputs C B A /Y7 /Y6 /Y5 Outputs /Y4 /Y3 /Y2 /Y1 /Y0 0 X X 1 1 1 1 1 1 1 1 Decoders 33 Decoders X 1 X 0 0 0 0 0 0 0 0 X X 1 0 0 0 0 0 0 0 0 X X X 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 X X X 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 34 Decoder cascading: 4-to-16 decoder to- More cascading: 5-to-32 decoder to- Two 3-to-8 3- to- Four 3-to-8 3- to- Decoders 35 Decoders 36 Combinational Logic Practices 9 CSE261 Spring 2008 Decoder applications Microprocessor memory systems selecting Implementing the Canonical Sum The binary decoder generates all minterms of n-variable logic function. nThe canonical sum of a logic functions is obtained by adding all minterms of that function: Match the order of input bits Activate Enable inputs different banks of memory Microprocessor input/output systems selecting different devices Microprocessor instruction decoding enabling Example: F = X,Y,Z (2,4,7) +5V 74x138 G1 G2A G2B X A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 F different functional units Memory chips enabling different rows of memory depending on address Y Z Decoder Applications Lots of other applications Decoder Applications 37 38 Logic design using Decoders Advantages: Flexibility Multiple-output Logic functions Multiple- Seven-Segment Displays SevenDisplays decimal numbers and some characters LED (Light Emitting Diode ) or LCD (Liquid Crystal Display) f a b g e d c Disadvantages: Complexity: for large number of inputs CommonAnode(CA) CommonAnode(CA) a b c d e f g CommonCathode(CC) CommonCathode(CC) a b c d e f g A practical alternative: PLD's PLD' requires Active Low inputs requires Active High inputs Decoder Applications 39 Decoder Applications 40 Combinational Logic Practices 10 CSE261 Spring 2008 Seven-Segment Decoders/Drivers SevenBCD Code Input D 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 0 1 1 1 b 1 1 1 1 1 0 0 1 1 1 c 1 1 0 1 1 1 1 1 1 1 MSI Seven-Segment Decoders Seven- Seven-Segment Code SevenOutput d 1 0 1 1 0 1 1 0 1 0 e 1 0 1 0 0 0 1 0 1 0 f 1 0 0 0 1 1 1 0 1 1 g 0 0 1 1 1 1 1 0 1 1 41 Decoder Applications 42 CC Driver : 74x49 74x49 CA Driver : 74x47 74x47 a BI a b c d e f g f g e d b A B C D c BI/RBO a RBI b LT c A d B e C f D g Decoder Applications 74x49 Driver Driving CC Seven-Segment Display Seven- Next time Encoders +5V 74x49 a BI A b c d e f g Three-state devices ThreeMultiplexers XOR gates Comparators Adders BCD Code B C D Decoder Applications 43 44 Combinational Logic Practices 11 ...
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