Lect6 - CSE261 Spring 2008 Encoders vs Decoders 1 2 3 4 Encoders Three-state Outputs ThreeMultiplexers XOR gates Decoder Encoder Inverse function

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Unformatted text preview: CSE261 Spring 2008 Encoders vs. Decoders 1. 2. 3. 4. Encoders Three-state Outputs ThreeMultiplexers XOR gates Decoder Encoder Inverse function of a Decoder. Outputs are less than inputs. output code input code ENCODER Converts input code words into output code words. CSE261 C5 #1 #1 Encoders CSE261 C5 #2 #2 Binary Encoders 2n-to-n toencoder: 2n inputs and n outputs. outputs. Example: n=3, 8-to-3 encoder Example: to1-out-of-2n out- ofInputs I0 1 0 0 0 0 0 0 0 I1 0 1 0 0 0 0 0 0 I2 0 0 1 0 0 0 0 0 I3 0 0 0 1 0 0 0 0 I4 0 0 0 0 1 0 0 0 I5 0 0 0 0 0 1 0 0 I6 0 0 0 0 0 0 1 0 I7 0 0 0 0 0 0 0 1 Binary encoder I0 I1 I2 I3 Y0 Y1 Y2 Binary Encoders Y2 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y0 = I4 + I5 + I6 + I7 Binary Code Outputs Y0 Y1 Y2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I4 I5 I6 I7 Limitations: Y2 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y0 = I4 + I5 + I6 + I7 Only one input can be activated IO has no effect Application: Handling multiple devices requests. But, no simultaneous requests. requests. Establishing priorities solve the problem of multiple requests. CSE261 C5 #3 #3 Encoders Encoders CSE261 C5 #4 #4 Encoders, MUX, XOR 1 CSE261 Spring 2008 Need priority in most applications 8-input priority encoder 1. Assign priorities to the inputs 2. When more than one input are asserted, the output generates the code of the input with the highest priority Encoders CSE261 C5 #5 #5 Encoders CSE261 C5 #6 #6 Priority-encoder logic equations PriorityH7 = I7 H6 = I6.I7' I6.I7' H5 = I5.I6'.I7' I5.I6' .I7' H4 = I4.I5'.I6'.I7' I4.I5' .I6' .I7' H3 = I3.I4'.I5'.I6'.I7' I3.I4' .I5' .I6' .I7' H2 = I2.I3'.I4'.I5'.I6'.I7' I2.I3' .I4' .I5' .I6' .I7' (Highest Priority) 74x148 8-input priority encoder 8- Priority encoder Priority Circuit I0 I1 I2 I3 I4 I5 I6 I7 I0 I1 I2 I3 I4 I5 I6 I7 H0 H1 H2 H3 H4 H5 H6 H7 IDLE Binary encoder I0 I1 I2 I3 I4 I5 I6 I7 IDLE Y0 Y1 Y2 A0 A1 A2 H1 = I1. I2'.I3'.I4'.I5'.I6'.I7' I2' .I3' .I4' .I5' .I6' H0 = I0.I1'. I2'.I3'.I4'.I5'.I6'.I7' I0.I1' I2' .I3' .I4' .I5' .I6' IDLE= I0'.I1'.I2'.I3'.I4'.I5'.I6'.I7' I0' .I1' .I2' .I3' .I4' .I5' .I6' A0 = I1 + I3 + I5 + I7 A1 = I2 + I3 + I6 + I7 A2 = I4 + I5 + I6 + I7 Encoders Active-low I/O ActiveEI: Enable Input GO: Got Something EO: Enable Output Encoders CSE261 C5 #8 #8 CSE261 C5 #7 #7 Encoders, MUX, XOR 2 CSE261 Spring 2008 74x148 circuit 74x148 Truth Table Encoders CSE261 C5 #9 #9 Encoders CSE261 C5 #10 #10 Encoder Application (Monitoring Unit) +5V BCD Encoder BCD encoder Alarm Signal Machine 1 Machine 2 Contoller Response Switch 0 I0 I1 I2 I3 Idle Y0 Y1 Y2 Y2 BI 74x49 a b c d e f g Machine Code Action Controller I4 I5 I6 I7 I8 I9 A B C D Encoder Switch 9 Machine 3 Encoders CSE261 C5 #11 #11 Encoders CSE261 C5 #12 #12 Encoders, MUX, XOR 3 CSE261 Spring 2008 Cascading priority encoders Three-state buffers ThreeOutput = LOW, HIGH, or Hi-Z. HiHi-Z: The output is floating (High Impedance) Hiwhen the enable input is deasserted 32-input priority encoder 32- The input is isolated from the output Application: Can tie multiple outputs together, if at most one at a time is driven. Controlling the access of a single line/bus by line/ multiple devices. Encoders CSE261 C5 #13 #13 Three-State Buffers Three- CSE261 C5 #14 #14 Different flavors 8 data sources sharing one line Active High Enable Active Low Enable Buffers Active High Enable Active Low Enable Inverters Three-State Buffers Three- CSE261 C5 #15 #15 Three-State Buffers Three- CSE261 C5 #16 #16 Encoders, MUX, XOR 4 CSE261 Spring 2008 Timing considerations SSI/MSI Three-State Buffers Three74x125: 4 independent buffers, Active Low enable 74x126: 4 independent buffers, Active High enable 74x540: 8 inverters with a common enable input 74x541: 8 buffers with a common enable input 74x240: 2 sets of 4 inverters with a common enable for each set 74x241: 2 sets of 4 buffers with a common enable for each set 74x245: Octal three-state transceiver three8 pairs of buffers connected in opposite directions Three-State Buffers Three- CSE261 C5 #17 #17 CSE261 C5 #18 #18 Three-state drivers Three- Driver application Three-State Buffers Three- CSE261 C5 #19 #19 Three-State Buffers Three- CSE261 C5 #20 #20 Encoders, MUX, XOR 5 CSE261 Spring 2008 Three-state transceiver Three- Transceiver application Three-State Buffers Three- CSE261 C5 #21 #21 Three-State Buffers Three- CSE261 C5 #22 #22 Multiplexers Multiplexing: transmitting large number of signals over a small number of channels or lines Digital multiplexer (MUX): selects one of many input lines and (MUX) directs it to a single output. Selection lines controls the selection of a particular input n selection lines, 2n inputs, single output Multiplexers Multiplexers CSE261 C5 #23 #23 Multiplexers CSE261 C5 #24 #24 Encoders, MUX, XOR 6 CSE261 Spring 2008 4-to-1 line multiplexer toS1 0 0 1 1 SO 0 1 0 1 Y I0 I1 I2 I3 I0 Logic Diagram of 4-to-1 Multiplexer 4- toI0 I1 Y I2 Inputs I1 I2 4x1 MUX S0 Y Output I3 I3 S1 S1 Select Multiplexers CSE261 C5 #25 #25 S0 Multiplexers CSE261 C5 #26 #26 Properties of different approaches 74x151: 8-to-1 MUX 74x151: 8- to74x251: 8-to-1 MUX with three-state output 8- tothree74x153: 4-to-1 2 bit MUX 4- to74x157: 2-to-1 4 bit MUX 2- to- 74x151 8-input multiplexer 8- Multiplexers CSE261 C5 #27 #27 Multiplexers CSE261 C5 #28 #28 Encoders, MUX, XOR 7 CSE261 Spring 2008 74x151 truth table Implementing Logic Functions n- variable logic function can be implemented using 2n-to-1 MUX toThe inputs variables are connected to the select input. The function value for each input combination (0 or 1) is connected to the corresponding input of the MUX Example: F = x,y (1,3) Row 0 1 2 3 X 0 0 1 1 Y 0 1 0 1 F 0 1 0 1 0 1 0 1 X Y CSE261 C5 #30 #30 I0 I1 I2 4x1 Y MUX S0 F I3 S1 Multiplexers CSE261 C5 #29 #29 Multiplexers Example: F = x,y,z (2,4,7) using 74x151 Functional Decomposition An effective way for using MUX to implement Logic Functions. +5V 74x151 EN Z Y X A B C D0 D1 D2 D3 D4 D5 D6 D7 Y Y F Row 0 1 2 3 4 5 6 7 X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F 0 0 1 0 1 0 0 1 n-row truth table can be implemented using n/2-to-1 MUX: n/2- toWrite the Logic function in terms of the least significant input variable. The truth table is reduced by one half. For 3-variable Logic Function, the decomposed truth table is: 3Row 0,1 2,3 4,5 6,7 X 0 0 1 1 Y 0 1 0 1 Z X X X X F F00(Z) F01(Z) F10(Z) F11(Z) F00(Z) F01(Z) F10(Z) F11(Z) X Y CSE261 C5 #32 #32 I0 I1 I2 4x1 Y MUX S0 F I3 S1 Multiplexers CSE261 C5 #31 #31 Multiplexers Encoders, MUX, XOR 8 CSE261 Spring 2008 Functional Decomposition Example Truth Table Row 0 1 2 3 4 5 6 7 X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F 0 0 1 0 1 0 0 1 F01(Z) = Z' Z' 0 F10(Z) = Z' Z' Z F11(Z) = Z X Y CSE261 C5 #33 #33 Demultiplexers Demultiplexer (DMUX) performs the opposite function of a MUX. DMUX) A digital Demultiplexer receives input data on a single input and transmits it on one of 2n possible outputs according to the value of the n select inputs MUX/DMUX are used in data transmission Source Destination BUS Decomposed Truth Table Row 0,1 F00(Z) = 0 2,3 4,5 6,7 X 0 0 1 1 Y 0 1 0 1 Z 0 X X X F 0 Z' Z' Z I0 I1 I2 A B 4x1 Y MUX S0 F C A B DMUX MUX I3 S1 C Select Multiplexers Select CSE261 C5 #34 #34 Multiplexers 1-to-4 DMUX toIN X X X X S1 0 0 1 1 S2 0 1 0 1 D0 IN 0 0 0 D1 0 IN 0 0 D2 0 0 IN 0 D3 0 0 0 IN S1 S0 D0 Using Decoders as DMUX A DMUX has the same structure of a Decoder with enable input. Decoder can be used as a DMUX by connecting the input data to the the enable input. Example: 2-to-4 Decoder can be used as 1-to-4 DMUX Example: 2- to1- toIN D2 D1 S1 0 0 1 1 S2 D0 D1 D2 D3 0 1 0 1 IN 0 0 0 0 IN 0 0 0 0 IN 0 0 0 0 IN S0 S1 INPUT I0 I1 EN Y0 Y1 Y2 Y3 D0 D1 D2 D3 D0 X X X X Input 1x4 D1 IN DMUX D2 S1 S0D3 Outputs IN D3 Select Multiplexers CSE261 C5 #35 #35 Multiplexers CSE261 C5 #36 #36 Encoders, MUX, XOR 9 CSE261 Spring 2008 2-input XOR gates Like an OR gate, but excludes the case where both inputs are 1. 1. XOR and XNOR symbols X 0 0 1 1 Y 0 1 0 1 XOR 0 1 1 0 XNOR 1 0 0 1 X Y = X 'Y + X Y ' ( X Y )' = X Y + X 'Y ' XOR CSE261 C5 #37 #37 XOR CSE261 C5 #38 #38 Gate-level XOR circuits GateNo direct realization with just a few transistors. SSI XOR 74x86: 4 XOR gates 74x266: 4 XNOR gates XOR CSE261 C5 #39 #39 XOR CSE261 C5 #40 #40 Encoders, MUX, XOR 10 CSE261 Spring 2008 Parity Circuit: Daisy Chain Parity tree Faster with balanced tree structure Odd Parity Circuit: The output is 1 if odd number of inputs are 1 Circuit: Even Parity Circuit: The output is 1 if even number of inputs are 1 Circuit: Used to generate and check parity bits in computer systems. Detects any single-bit error singleXOR CSE261 C5 #41 #41 XOR CSE261 C5 #42 #42 XOR Example: Daisy-Chain Structure DaisyI0 I1 I2 I3 I0 I1 I2 I3 Next time Tree structure EVEN ODD EVEN ODD 1. 2. 3. Comparators Adders Multipliers Read-only memories (ROMs) Read- Input: 1101 Even Parity output: 0 Odd Parity output: 1 4. CSE261 C5 #43 #43 CSE261 C5 #44 #44 Encoders, MUX, XOR 11 ...
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This note was uploaded on 05/08/2008 for the course CSE 261 taught by Professor Ercanli during the Spring '08 term at Syracuse.

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