lect8 - CSE 261 April 2008 A Generic Digital Processor...

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Unformatted text preview: CSE 261 April 2008 A Generic Digital Processor Building Blocks for Digital Architectures RAM, ROM, Buffers, Shift registers Sequential Logic Design Principles INPUT - OUTPUT MEMORY CPU CONTROL DATAPATH Finite state machine: PLA, Counters, ... Sequential Logic C7 #1 #1 Interconnect: Switches, Arbiters, Bus, ... Arithmetic Unit: Adder, multiplier, shifter, comparator, ... Sequential Logic C7 #2 #2 Sequential Logic C7 #3 #3 Sequential Logic C7 #4 #4 Analysis of State Machines CSE 261 April 2008 Outline 1. 2. Logic Devices Combinational Logic: Current output depends on current input only Bistable Logic Elements and Metastability What are latches and flip-flops? flip- flops? Gates Decoders Multiplexers ALUs Combinational Logic Types, Function, Structure 3. Analysis of State Machines Sequential Logic: Current output depends on past inputs as well as current input; thus has a memory (state). state). General structure, Analysis procedure Latches and Flip-Flops FlipState Machines Counters Shift Registers Sequential Logic Memory Sequential Logic C7 #6 #6 4. Synthesis of State Machines State minimization, State assignment Sequential Logic C7 #5 #5 Sequential Logic Definitions STATE: STATE: A Clock Characteristics Clock - the master timing element behind the state changes. State change Frequency = 1/Period tH collection of state variables whose values contain all the information about the past values necessary to account for future behavior. (e.g. a TV tuner with up/down button) with n binary state variables has 2n possible states usually synchronized with a system clock Circuit Active High Period tL Changes Duty Cycle = tH/Period Period: time between successive transitions in the same direction Digital sequential logic Also State change Duty Cycle: the percentage of time that a clock is at its assertion level. = tL/Period Sequential Logic C7 #8 #8 known as a finite state machine (FSM). Active Low Sequential Logic C7 #7 #7 tL Period tH Definitions Definitions Analysis of State Machines CSE 261 April 2008 Types of Sequential Logic A Feedback Sequential Circuit uses gates with feedback to form memory elements (latches and flip/flops) used in state machines. Bistable Element The simplest possible feedback sequential logic circuit is: A Clocked Synchronous State Machine uses clocked flip-flops to form useful sequential logic functions or flipapplication. It is bistable because it has two stable states: State 1: If Q (Q=Vout1=Vin2) is high, the bottom inverter output (/Q =Vout2=Vin1) is low, which keeps the top inverter output Q high. State 2: If Q is low, the bottom inverter output /Q is high, which keeps the top inverter output Q low. Definitions Sequential Logic C7 #9 #9 Bistable Logic Elements Sequential Logic C7 #10 #10 Bistable Element The simplest sequential circuit Two states One state variable, Q HIGH LOW Bistable Element The simplest sequential circuit Two states One state variable, Q LOW HIGH LOW HIGH HIGH LOW Bistable Logic Elements Sequential Logic C7 #11 #11 Bistable Logic Elements Sequential Logic C7 #12 #12 Analysis of State Machines CSE 261 April 2008 Analog Analysis of Bistable Top Inverter alone Q Vout1 Bottom Inverter alone Vin2 Bistable and Metastability There are not two stable states, but three (a problem!) (a problem!) Metastable point occurs when both outputs are halfway between high and low Vin1 Complete Bistable Vout1 =Vin2 Stable High Metastable Stable Low Vout2 /Q not a valid logic level!!! Could last forever, but noise pushes towards a stable state. Vin1 =Vout2 Metastability Sequential Logic C7 #13 #13 Metastability Sequential Logic C7 #14 #14 Metastability Metastability? Metastability? All real systems are subject to it Problems are caused by "asynchronous inputs" that do not inputs" meet flip-flop setup and hold times. flip- Especially severe in high-speed systems high Since clock periods are so short, `metastability resolution time' can be longer than one clock period. time' Many digital designers, products, and companies have been burned by this phenomenon. phenomenon. Metastability Sequential Logic C7 #15 #15 Metastability Sequential Logic C7 #16 #16 Analysis of State Machines CSE 261 April 2008 Latches and Flip-flops? FlipCommon feedback sequential circuits Latch Single-bit Single Changes Types of Latches and Flip-flops FlipLatches S-R Latch /S-/R Latch /S S-R Latch with Enable D Latch Flip-flops Flip Edge-Triggered D Flip-Flop EdgeFlip Master/Slave S-R Flip-Flop S- Flip Master/Slave J-K Flip-Flop J- Flip Edge-Triggered J-K Flip-Flop Edge J- Flip T Flip-Flop FlipLatches Sequential Logic C7 #18 #18 storage (memory) state at any time due to input change Flip-flop Flip Also single-bit storage singlestate ONLY when a clock edge or pulse is applied Changes Latches Sequential Logic C7 #17 #17 Back to the bistable.... bistable... Symbol Set Reset S R Q Q S-R Latch Q /Q Hold Reset Function Table S 0 0 1 1 R 0 1 0 1 Q Last Q 0 1 0 /Q Last /Q 1 0 0 Schematic R Set Q /Q ILLEGAL How to control it? Screwdriver Control inputs S-R latch S Consider: 1. Timing Diagram 2. Propagation delay 3. Minimum pulse width 4. Oscillation Latches Sequential Logic C7 #19 #19 Latches Sequential Logic C7 #20 #20 Analysis of State Machines CSE 261 April 2008 S-R latch operation 0 1 0 1 Schematic R S-R latch timing parameters Q /Q S 0 0 ? 0 Propagation delay Minimum pulse width ? 0 Metastability is possible if S and R are negated simultaneously. Latches Sequential Logic C7 #21 #21 Latches Sequential Logic C7 #22 #22 S-R latch symbols S-R latch using NAND gates:/S-/R Latch gates:/S- Function Table /S Illegal Set Reset Hold Latches Sequential Logic C7 #23 #23 Latches /R 0 1 0 1 Q 1 1 0 Last Q /Q 1 0 1 Last /Q 0 0 1 1 Sequential Logic C7 #24 #24 Analysis of State Machines CSE 261 April 2008 S-R Latch with Enable /S /R 0 1 0 1 x C 1 1 1 1 0 Q Last Q 0 1 1 Last Q /Q Last /Q 1 0 1 Last /Q D Latch D C Q Q S C R Q Q 0 0 1 1 x Store a data bit, not set/reset Only sensitive to S and R when enabled (C=1) Same oscillation problem Latches Sequential Logic C7 #25 #25 Latches `Transparent latch' latch' Setup and Hold time Sequential Logic C7 #26 #26 D-latch timing parameters Propagation delay from C or D Positive-Edge-Triggered D Flip-Flop Positive- EdgeFlip- D should not change during: tsetup (before C edge)+thold (after C edge) Latches Setup time HoldSequential Logic C7 #27 time #27 Flip-Flop Flip- Sequential Logic C7 #28 #28 Analysis of State Machines CSE 261 April 2008 D flip-flop timing parameters flipPropagation delay from CLK D flip-flop versus latch flip- D should not change during: tsetup (before C edge)+thold (after C edge) Setup time Flip-Flop Flip- Hold time Sequential Logic C7 #29 #29 Flip-Flop FlipSequential Logic C7 #30 #30 Other D flip-flop variations flipNegative-edge Negativetriggered Scan flip-flops -- for testing flip- Clock Enable TE = 0 TE = 1 Scan normal operation test operation All of the flip-flops are hooked together in a daisy chain from flipexternal test input TI. Load up ("scan in") a test pattern, do one normal operation, (" in" shift out ("scan out") result on TO. (" out" Sequential Logic C7 #31 #31 Flip-Flop FlipSequential Logic C7 #32 #32 Flip-Flop Flip- Analysis of State Machines CSE 261 April 2008 Asynchronous Inputs Most flip-flops have two asynchronous inputs flipPreset and Reset (or Clear) Directly set or reset the /S-/R latches /SOperate independent of clock Good design practice: NEVER use asynchronous inputs for logic functions, only for system initialization to a known state Master/Slave S-R Flip-Flop S- FlipS R X 0 0 1 1 C 0 Q Last Q Last Q 0 1 Undef /Q Last /Q Last /Q 1 0 Undef S C R Q Q X 0 0 1 1 S C R Q Q S C R Q Q Flip-Flop Flip- Sequential Logic C7 #33 #33 Flip-Flop Flip- "Pulse-triggered" S-R flip-flop Pulse- triggered" flipPulse-catching behavior Pulse- Sequential Logic C7 #34 #34 J-K flip-flops flip- T (toggle) Flip-Flop FlipT flip-flop changes state on every clock tick. flipImportant for counters Not used much anymore Flip-Flop FlipSequential Logic C7 #35 #35 Flip-Flop FlipSequential Logic C7 #36 #36 Analysis of State Machines CSE 261 April 2008 Sequential PALs 16R8 Analysis of State Machines Characteristic Equations Describe the next state of a flip-flop as function of current flipstate and inputs: QN = f (Q, inputs) Derived from basic function table for a given flip-flop type flip- Sequential PALs Sequential Logic C7 #37 #37 State Machine Analysis Sequential Logic C7 #38 #38 Characteristic Equations Input D 0 0 1 1 Present state Q 0 1 0 1 Next state Input S 0 0 0 1 1 R 0 0 1 0 1 Present state Q 0 1 X X X Next state J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Characteristic Equations Q 0 1 0 1 0 1 0 1 Q* 0 1 0 0 1 1 1 0 Q* 0 0 1 1 Q* 0 1 0 1 X hold reset set toggle EN 0 0 1 1 Q 0 1 0 1 Q* 0 1 1 0 Characteristic Equation: Q* = D Characteristic Equation: Q* = S + R' Q R' Characteristic Equation: Q* = J Q' + K' Q Q' K' State Machine Analysis Characteristic Equation: Q* = EN Q' + EN' Q Q' EN' State Machine Analysis Sequential Logic C7 #39 #39 Sequential Logic C7 #40 #40 Analysis of State Machines CSE 261 April 2008 Characteristic Equations Summary Device Type S-R latch D latch Edge-triggered D flip-flop EdgeflipMaster/slave S-R flip-flop S- flipMaster/slave J-K flip-flop J- flipEdge-triggered J-K flip-flop EdgeJ- flipT flip-flop flipT flip-flop with enable flip- Clocked Synchronous State-machine StateAnalysis Analysis Characteristic Equation Q* = S + R' Q R' Q* = D Q* = D Q* = S + R' Q R' Q* = J Q' + K' Q Q' K' Q* = J Q' + K' Q Q' K' Q* = Q' Q' Q* = EN Q' + EN' Q Q' EN' How does a given circuit work? What does it do? How do input sequences map to output sequences? Mealy Machine Next state = F (current state, inputs) Output = G (current state, inputs) Moore Machine Next state = F (current state, inputs) Output = G (current state) Sequential Logic C7 #42 #42 State Machine Analysis Sequential Logic C7 #41 #41 State Machine Analysis Difference between Mealy & Moore Machines Mealy Machine Basic Analysis of State Machines Determine next-state and output functions F and G next- inputs NextNextState Logic next_state State Registers current_state Output Logic outputs Use F and G to construct a state table Draw a state diagram that represents the state table in graphical form clock Moore Machine inputs NextNextState Logic next_state State Registers current_state Output Logic outputs clock State Machine Analysis Sequential Logic C7 #43 #43 State Machine Analysis Sequential Logic C7 #44 #44 Analysis of State Machines CSE 261 April 2008 Detailed Analysis of State Machines Example 1 - State Machine with T flip-flops flipX X E0 Find flip-flop input excitation equations, D = f1 (state, inputs) flipequations, Substitute excitation equations into flip-flop characteristic equations, flipgiving transition equations, Q* = f2 (state, inputs) equations, EN Q Q0 Q0* = E0 Q0' + E0' Q0 Q0' E0' T C Output Equation: Construct a transition table from transition equations Find output equations, OUT = g (state) or g (state, inputs) equations, Add outputs to to transition table to form transition/output table Name states in transition/output table, giving state/output table Draw a state diagram and timing diagram from state/output table E1 Z = Q0 + Q1 Q0 CLK EN Q T Q1 Q1* =E1 Q1'+ E1' Q1 Q1' E1' C RESET X.Q0 Characteristic Equation for T: Q* = EN. Q' + EN' Q Q' EN' State Machine Analysis Sequential Logic C7 #45 #45 State Machine Analysis Sequential Logic C7 #46 #46 Example 1 Transition-State/Output Table TransitionX Q1Q0 A=00 B=01 C=10 D=11 0 00 01 10 11 1 01 10 11 00 Z 0 1 1 1 X S 0 A B C D 1 B C D A Z 0 1 1 1 A B C D Example 1 - State Diagram X=0 Output Equation: Z = Q0 + Q1 Moore Machine X S A B C D 0 A B C D 1 B C D A Z 0 1 1 1 A Z=0 X=1 B Z=1 X=1 X=0 X=1 Q1*Q0*, Z X=0 D Z=1 X=1 C Z=1 X=0 S* Transition Equations: Q0* = X Q0' + X' Q0 Q0' X' Q1* = X Q0 Q1' + X' Q1 + Q0' Q1 Q1' X' Q0' State Machine Analysis S* Sequential Logic C7 #47 #47 State Machine Analysis Sequential Logic C7 #48 #48 Analysis of State Machines CSE 261 April 2008 Example 1 - Timing diagram Example 2 - State Machine with D Flip-flops FlipExcitation Equations: D0 = X Y' Q2'; D1 = X Q0; D2 = Y' +Q1 Y' Q2' Y' CLK X RESET Y /Q2 D0 Q0 D CLK Q Q Z1 Z1 = X Q0 + Q1' (Mealy) Q1' X D1 Q0 STATE Q1 Q0 A A B C C D D A D CLK Q Q Q1 /Z2= /Z2= (Q1 Q2)' (Moore) Q2)' Q2 /Q2 /Z2 D2 Z Q1 CLK D CLK Q Q A mealy machine Output Logic G Sequential Logic C7 #50 #50 Excitation Logic F State Machine Analysis Sequential Logic C7 #49 #49 State Machine Analysis State Memory Example 2 - Equations Characteristic Equation for D flip-flop: Q* = D flipExcitation Equations: Next State Equations: Example 2 - Transition / Output table XY Q2 Q1 Q0 A=000 B=001 C=010 D=011 E=100 F=101 G=110 00 100, 11 100, 11 100, 01 100, 01 100, 11 100, 11 100, 00 100, 00 01 000, 11 000, 11 100, 01 100, 01 000, 11 000, 11 100, 00 100, 00 11 000, 11 010, 11 100, 01 110, 11 000, 11 010, 11 100, 00 110, 10 10 101, 11 111, 11 101, 01 111, 11 100, 11 110, 11 100, 00 110, 10 D0 = X Y' Q2' Y' Q2' D1 = X Q0 D2 = Y' + Q1 Output Equations: Q0* = X Y' Q2' Y' Q2' Q1* = X Q0 Q2* = Y' + Q1 Y' Z1 = X Q0 + Q1' (Mealy) Q1' /Z2= (Q1 Q2)' (Moore) /Z2= Q2)' A mealy machine H=111 Q2* Q1* Q0*, Z1 /Z2 Q0* = X Y' Q2' Y' Q2' Q1* = X Q0 Q2* = Y' + Q1 Y' State Machine Analysis Sequential Logic C7 #51 #51 State Machine Analysis Z1 = X Q0 + Q1' Q1' /Z2= (Q1 Q2)' /Z2= Q2)' Sequential Logic C7 #52 #52 Analysis of State Machines CSE 261 April 2008 Example 2 - State / Output table XY S A B C D E F G H Example 2 - State Diagram Y, (11) X'Y, (11) B XY, (11) 00 E, 11 E, 11 E, 01 E, 01 E, 11 E, 11 E, 00 E, 00 01 A, 11 A, 11 E, 01 E, 01 A, 11 A, 11 E, 00 E, 00 11 A, 11 C, 11 E, 01 G, 11 A, 11 C, 11 E, 00 G, 10 10 F, 11 H, 11 F, 01 H, 11 E, 11 G, 11 E, 00 G, 10 S A XY', (11) XY' A X'Y', (11) C X'Y', (11) D H XY', (11) XY' G F A, 11 F, 11 E S*, Z1 /Z2 XY = 00 XY = 01 XY = 11 XY = 10 E, 11 A, 11 B State Machine Analysis Sequential Logic C7 #53 #53 E, 11 A, 11 C, 11 H, 11 Sequential Logic C7 #54 #54 State Machine Analysis Example 3 - Circuit and Equations Example 3 - Tables Excitation/Output Tables: X Y X CLK D Q Q Q Moore X 1 1 0 Q 0 1 0 0 0 Q* Z 0 1 Q 0 1 0 0,0 0,1 1 1,1 0,0 Mealey Q*, Y State/Output Tables: X Moore Excitation: D = X Q' = Q* Output: Q = Q Mealy Excitation: D = X Q' = Q* Output: Y=XQ S A B 0 A A Q* 1 B A Z 0 1 X S A B 0 A, 0 A, 1 1 B, 1 A, 0 S*, Y Sequential Logic C7 #56 #56 State Machine Analysis Sequential Logic C7 #55 #55 State Machine Analysis Analysis of State Machines CSE 261 April 2008 Example 3 - State Diagrams input X=1 X= 0 A Z=0 B Z=1 X=0,1 State Output X= 0 (Z = 0) X=1 (Z = 1) A X=0,1 (Z = 0) B State Machine Analysis Sequential Logic C7 #57 #57 Analysis of State Machines Mealey Moore ...
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This note was uploaded on 05/08/2008 for the course CSE 261 taught by Professor Ercanli during the Spring '08 term at Syracuse.

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